[PATCH] D100127: [RISCV][Clang] Add some RVV Permutation intrinsic functions.

[Zakk Chen via Phabricator via cfe-commits]

khchen created this revision.
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Support the following instructions.

1. Vector Slide Instructions
2. Vector Register Gather Instructions
3. Vector Compress Instruction

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen at sifive.com>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D100127

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1down.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1up.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c