[clang] 5f6b3d1 - [RISCV] Use multiclass inheritance to simplify some of riscv_vector.td. NFCI
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Wed Apr 7 17:36:05 PDT 2021
Author: Craig Topper
Date: 2021-04-07T17:33:21-07:00
New Revision: 5f6b3d1833fdf20e18a3c8bf3ede7b5060130f73
URL: https://github.com/llvm/llvm-project/commit/5f6b3d1833fdf20e18a3c8bf3ede7b5060130f73
DIFF: https://github.com/llvm/llvm-project/commit/5f6b3d1833fdf20e18a3c8bf3ede7b5060130f73.diff
LOG: [RISCV] Use multiclass inheritance to simplify some of riscv_vector.td. NFCI
We don't need to instantiate single multiclasses inside of
other multiclasses. We can use inheritance and save writing 'defm ""'.
Reviewed By: khchen
Differential Revision: https://reviews.llvm.org/D100074
Added:
Modified:
clang/include/clang/Basic/riscv_vector.td
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 98beebf25da8c..9b8a0d87de5cc 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -217,127 +217,109 @@ multiclass RVVBuiltinSet<string intrinsic_name, string type_range,
// IntrinsicTypes is output, op0, op1 [-1, 0, 1]
multiclass RVVOutOp0Op1BuiltinSet<string intrinsic_name, string type_range,
- list<list<string>> suffixes_prototypes> {
- defm NAME : RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes,
+ list<list<string>> suffixes_prototypes>
+ : RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes,
[-1, 0, 1]>;
-}
// IntrinsicTypes is output, op1 [-1, 1]
multiclass RVVOutOp1BuiltinSet<string intrinsic_name, string type_range,
- list<list<string>> suffixes_prototypes> {
- defm "" : RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [-1, 1]>;
-}
+ list<list<string>> suffixes_prototypes>
+ : RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [-1, 1]>;
multiclass RVVOp0Op1BuiltinSet<string intrinsic_name, string type_range,
- list<list<string>> suffixes_prototypes> {
- defm "" : RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [0, 1]>;
-}
+ list<list<string>> suffixes_prototypes>
+ : RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [0, 1]>;
multiclass RVVOutOp1Op2BuiltinSet<string intrinsic_name, string type_range,
- list<list<string>> suffixes_prototypes> {
- defm "" : RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [-1, 1, 2]>;
-}
+ list<list<string>> suffixes_prototypes>
+ : RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [-1, 1, 2]>;
-multiclass RVVSignedBinBuiltinSet {
- defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
- [["vv", "v", "vvv"],
- ["vx", "v", "vve"]]>;
-}
+multiclass RVVSignedBinBuiltinSet
+ : RVVOutOp1BuiltinSet<NAME, "csil",
+ [["vv", "v", "vvv"],
+ ["vx", "v", "vve"]]>;
-multiclass RVVUnsignedBinBuiltinSet {
- defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
- [["vv", "Uv", "UvUvUv"],
- ["vx", "Uv", "UvUvUe"]]>;
-}
+multiclass RVVUnsignedBinBuiltinSet
+ : RVVOutOp1BuiltinSet<NAME, "csil",
+ [["vv", "Uv", "UvUvUv"],
+ ["vx", "Uv", "UvUvUe"]]>;
-multiclass RVVIntBinBuiltinSet {
- defm "" : RVVSignedBinBuiltinSet;
- defm "" : RVVUnsignedBinBuiltinSet;
-}
+multiclass RVVIntBinBuiltinSet
+ : RVVSignedBinBuiltinSet,
+ RVVUnsignedBinBuiltinSet;
-multiclass RVVSignedShiftBuiltinSet {
- defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
- [["vv", "v", "vvUv"],
- ["vx", "v", "vvz"]]>;
-}
+multiclass RVVSignedShiftBuiltinSet
+ : RVVOutOp1BuiltinSet<NAME, "csil",
+ [["vv", "v", "vvUv"],
+ ["vx", "v", "vvz"]]>;
-multiclass RVVUnsignedShiftBuiltinSet {
- defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
- [["vv", "Uv", "UvUvUv"],
- ["vx", "Uv", "UvUvz"]]>;
-}
+multiclass RVVUnsignedShiftBuiltinSet
+ : RVVOutOp1BuiltinSet<NAME, "csil",
+ [["vv", "Uv", "UvUvUv"],
+ ["vx", "Uv", "UvUvz"]]>;
-multiclass RVVShiftBuiltinSet {
- defm "" : RVVSignedShiftBuiltinSet;
- defm "" : RVVUnsignedShiftBuiltinSet;
-}
+multiclass RVVShiftBuiltinSet
+ : RVVSignedShiftBuiltinSet,
+ RVVUnsignedShiftBuiltinSet;
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
- multiclass RVVSignedNShiftBuiltinSet {
- defm "" : RVVOutOp0Op1BuiltinSet<NAME, "csil",
+ multiclass RVVSignedNShiftBuiltinSet
+ : RVVOutOp0Op1BuiltinSet<NAME, "csil",
[["wv", "v", "vwUv"],
["wx", "v", "vwz"]]>;
- }
- multiclass RVVUnsignedNShiftBuiltinSet {
- defm "" : RVVOutOp0Op1BuiltinSet<NAME, "csil",
+ multiclass RVVUnsignedNShiftBuiltinSet
+ : RVVOutOp0Op1BuiltinSet<NAME, "csil",
[["wv", "Uv", "UvUwUv"],
["wx", "Uv", "UvUwz"]]>;
- }
-}
-
-multiclass RVVIntTerBuiltinSet {
- defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
- [["vv", "v", "vvvv"],
- ["vx", "v", "vvev"],
- ["vv", "Uv", "UvUvUvUv"],
- ["vx", "Uv", "UvUvUeUv"]]>;
}
-multiclass RVVCarryinBuiltinSet {
- defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
- [["vvm", "v", "vvvm"],
- ["vxm", "v", "vvem"],
- ["vvm", "Uv", "UvUvUvm"],
- ["vxm", "Uv", "UvUvUem"]]>;
-}
-
-multiclass RVVCarryOutInBuiltinSet<string intrinsic_name> {
- defm "" : RVVOp0Op1BuiltinSet<intrinsic_name, "csil",
- [["vvm", "vm", "mvvm"],
- ["vxm", "vm", "mvem"],
- ["vvm", "Uvm", "mUvUvm"],
- ["vxm", "Uvm", "mUvUem"]]>;
-}
-
-multiclass RVVSignedMaskOutBuiltinSet {
- defm "" : RVVOp0Op1BuiltinSet<NAME, "csil",
- [["vv", "vm", "mvv"],
- ["vx", "vm", "mve"]]>;
-}
-
-multiclass RVVUnsignedMaskOutBuiltinSet {
- defm "" : RVVOp0Op1BuiltinSet<NAME, "csil",
- [["vv", "Uvm", "mUvUv"],
- ["vx", "Uvm", "mUvUe"]]>;
-}
-
-multiclass RVVIntMaskOutBuiltinSet {
- defm "" : RVVSignedMaskOutBuiltinSet;
- defm "" : RVVUnsignedMaskOutBuiltinSet;
-}
-
-multiclass RVVFloatingBinBuiltinSet {
- defm "" : RVVOutOp1BuiltinSet<NAME, "fd",
- [["vv", "v", "vvv"],
- ["vf", "v", "vve"]]>;
-}
-
-multiclass RVVIntExt<string intrinsic_name, string suffix, string prototype,
- string type_range> {
- let IRName = intrinsic_name, IRNameMask = intrinsic_name # "_mask",
- MangledName = NAME, IntrinsicTypes = [-1, 0] in {
- def "" : RVVBuiltin<suffix, prototype, type_range>;
- }
+multiclass RVVIntTerBuiltinSet
+ : RVVOutOp1BuiltinSet<NAME, "csil",
+ [["vv", "v", "vvvv"],
+ ["vx", "v", "vvev"],
+ ["vv", "Uv", "UvUvUvUv"],
+ ["vx", "Uv", "UvUvUeUv"]]>;
+
+multiclass RVVCarryinBuiltinSet
+ : RVVOutOp1BuiltinSet<NAME, "csil",
+ [["vvm", "v", "vvvm"],
+ ["vxm", "v", "vvem"],
+ ["vvm", "Uv", "UvUvUvm"],
+ ["vxm", "Uv", "UvUvUem"]]>;
+
+multiclass RVVCarryOutInBuiltinSet<string intrinsic_name>
+ : RVVOp0Op1BuiltinSet<intrinsic_name, "csil",
+ [["vvm", "vm", "mvvm"],
+ ["vxm", "vm", "mvem"],
+ ["vvm", "Uvm", "mUvUvm"],
+ ["vxm", "Uvm", "mUvUem"]]>;
+
+multiclass RVVSignedMaskOutBuiltinSet
+ : RVVOp0Op1BuiltinSet<NAME, "csil",
+ [["vv", "vm", "mvv"],
+ ["vx", "vm", "mve"]]>;
+
+multiclass RVVUnsignedMaskOutBuiltinSet
+ : RVVOp0Op1BuiltinSet<NAME, "csil",
+ [["vv", "Uvm", "mUvUv"],
+ ["vx", "Uvm", "mUvUe"]]>;
+
+multiclass RVVIntMaskOutBuiltinSet
+ : RVVSignedMaskOutBuiltinSet,
+ RVVUnsignedMaskOutBuiltinSet;
+
+multiclass RVVFloatingBinBuiltinSet
+ : RVVOutOp1BuiltinSet<NAME, "fd",
+ [["vv", "v", "vvv"],
+ ["vf", "v", "vve"]]>;
+
+class RVVIntExt<string intrinsic_name, string suffix, string prototype,
+ string type_range>
+ : RVVBuiltin<suffix, prototype, type_range> {
+ let IRName = intrinsic_name;
+ let IRNameMask = intrinsic_name # "_mask";
+ let MangledName = NAME;
+ let IntrinsicTypes = [-1, 0];
}
defvar TypeList = ["c","s","i","l","f","d"];
@@ -520,16 +502,16 @@ defm vrsub : RVVOutOp1BuiltinSet<"vrsub", "csil",
// 12.3. Vector Integer Extension
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
- defm vsext_vf2 : RVVIntExt<"vsext", "w", "wv", "csi">;
- defm vzext_vf2 : RVVIntExt<"vzext", "Uw", "UwUv", "csi">;
+ def vsext_vf2 : RVVIntExt<"vsext", "w", "wv", "csi">;
+ def vzext_vf2 : RVVIntExt<"vzext", "Uw", "UwUv", "csi">;
}
let Log2LMUL = [-3, -2, -1, 0, 1] in {
- defm vsext_vf4 : RVVIntExt<"vsext", "q", "qv", "cs">;
- defm vzext_vf4 : RVVIntExt<"vzext", "Uq", "UqUv", "cs">;
+ def vsext_vf4 : RVVIntExt<"vsext", "q", "qv", "cs">;
+ def vzext_vf4 : RVVIntExt<"vzext", "Uq", "UqUv", "cs">;
}
let Log2LMUL = [-3, -2, -1, 0] in {
- defm vsext_vf8 : RVVIntExt<"vsext", "o", "ov", "c">;
- defm vzext_vf8 : RVVIntExt<"vzext", "Uo", "UoUv", "c">;
+ def vsext_vf8 : RVVIntExt<"vsext", "o", "ov", "c">;
+ def vzext_vf8 : RVVIntExt<"vzext", "Uo", "UoUv", "c">;
}
// 12.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
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