[PATCH] D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai updated this revision to Diff 333806.
HsiangKai added a comment.

Use 'vr' for vector registers and 'vm' for vector mask registers.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98616/new/

https://reviews.llvm.org/D98616

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c

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