[PATCH] D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.

Kito Cheng via Phabricator via cfe-commits cfe-commits at lists.llvm.org
Mon Mar 15 07:04:38 PDT 2021

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kito-cheng added a comment.

GCC use `vr` for vector register and `vm` for vector mask register.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D98616/new/

https://reviews.llvm.org/D98616

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