[PATCH] D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added a comment.

This seems like the obvious choice for the constraint, but it would be good to ensure there's consensus with GCC people, especially since their assembly constraints are intimately tied to their instruction patterns (or, really, the assembly constraints just expose those and we pretend to be GCC) so they have less flexibility than us.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D98616/new/

https://reviews.llvm.org/D98616