[clang] 394a4d0 - [AArch64] Add missing intrinsics for vcls
Jingu Kang via cfe-commits
cfe-commits at lists.llvm.org
Wed Mar 3 02:36:37 PST 2021
Author: JinGu Kang
Date: 2021-03-03T10:17:56Z
New Revision: 394a4d04333e8b26ff581eb1f6c56a6e50a157e4
URL: https://github.com/llvm/llvm-project/commit/394a4d04333e8b26ff581eb1f6c56a6e50a157e4
DIFF: https://github.com/llvm/llvm-project/commit/394a4d04333e8b26ff581eb1f6c56a6e50a157e4.diff
LOG: [AArch64] Add missing intrinsics for vcls
Differential Revision: https://reviews.llvm.org/D97775
Added:
Modified:
clang/include/clang/Basic/arm_neon.td
clang/test/CodeGen/aarch64-neon-misc.c
clang/test/CodeGen/arm_neon_intrinsics.c
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/arm_neon.td b/clang/include/clang/Basic/arm_neon.td
index 0b0105c665f5..5360729db307 100644
--- a/clang/include/clang/Basic/arm_neon.td
+++ b/clang/include/clang/Basic/arm_neon.td
@@ -646,7 +646,7 @@ def VABS : SInst<"vabs", "..", "csifQcQsQiQf">;
def VQABS : SInst<"vqabs", "..", "csiQcQsQi">;
def VNEG : SOpInst<"vneg", "..", "csifQcQsQiQf", OP_NEG>;
def VQNEG : SInst<"vqneg", "..", "csiQcQsQi">;
-def VCLS : SInst<"vcls", "..", "csiQcQsQi">;
+def VCLS : SInst<"vcls", "S.", "csiUcUsUiQcQsQiQUcQUsQUi">;
def VCLZ : IInst<"vclz", "..", "csiUcUsUiQcQsQiQUcQUsQUi">;
def VCNT : WInst<"vcnt", "..", "UccPcQUcQcQPc">;
def VRECPE : SInst<"vrecpe", "..", "fUiQfQUi">;
diff --git a/clang/test/CodeGen/aarch64-neon-misc.c b/clang/test/CodeGen/aarch64-neon-misc.c
index 5517fe3dc411..4f85f67cdaec 100644
--- a/clang/test/CodeGen/aarch64-neon-misc.c
+++ b/clang/test/CodeGen/aarch64-neon-misc.c
@@ -1432,6 +1432,13 @@ int8x8_t test_vcls_s8(int8x8_t a) {
return vcls_s8(a);
}
+// CHECK-LABEL: @test_vcls_u8(
+// CHECK: [[VCLS_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.cls.v8i8(<8 x i8> %a)
+// CHECK: ret <8 x i8> [[VCLS_V_I]]
+int8x8_t test_vcls_u8(uint8x8_t a) {
+ return vcls_u8(a);
+}
+
// CHECK-LABEL: @test_vclsq_s8(
// CHECK: [[VCLSQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.cls.v16i8(<16 x i8> %a)
// CHECK: ret <16 x i8> [[VCLSQ_V_I]]
@@ -1439,6 +1446,13 @@ int8x16_t test_vclsq_s8(int8x16_t a) {
return vclsq_s8(a);
}
+// CHECK-LABEL: @test_vclsq_u8(
+// CHECK: [[VCLSQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.cls.v16i8(<16 x i8> %a)
+// CHECK: ret <16 x i8> [[VCLSQ_V_I]]
+int8x16_t test_vclsq_u8(uint8x16_t a) {
+ return vclsq_u8(a);
+}
+
// CHECK-LABEL: @test_vcls_s16(
// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
// CHECK: [[VCLS_V1_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.cls.v4i16(<4 x i16> %a)
@@ -1448,6 +1462,15 @@ int16x4_t test_vcls_s16(int16x4_t a) {
return vcls_s16(a);
}
+// CHECK-LABEL: @test_vcls_u16(
+// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
+// CHECK: [[VCLS_V1_I:%.*]] = call <4 x i16> @llvm.aarch64.neon.cls.v4i16(<4 x i16> %a)
+// CHECK: [[VCLS_V2_I:%.*]] = bitcast <4 x i16> [[VCLS_V1_I]] to <8 x i8>
+// CHECK: ret <4 x i16> [[VCLS_V1_I]]
+int16x4_t test_vcls_u16(uint16x4_t a) {
+ return vcls_u16(a);
+}
+
// CHECK-LABEL: @test_vclsq_s16(
// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
// CHECK: [[VCLSQ_V1_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.cls.v8i16(<8 x i16> %a)
@@ -1457,6 +1480,15 @@ int16x8_t test_vclsq_s16(int16x8_t a) {
return vclsq_s16(a);
}
+// CHECK-LABEL: @test_vclsq_u16(
+// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
+// CHECK: [[VCLSQ_V1_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.cls.v8i16(<8 x i16> %a)
+// CHECK: [[VCLSQ_V2_I:%.*]] = bitcast <8 x i16> [[VCLSQ_V1_I]] to <16 x i8>
+// CHECK: ret <8 x i16> [[VCLSQ_V1_I]]
+int16x8_t test_vclsq_u16(uint16x8_t a) {
+ return vclsq_u16(a);
+}
+
// CHECK-LABEL: @test_vcls_s32(
// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8>
// CHECK: [[VCLS_V1_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.cls.v2i32(<2 x i32> %a)
@@ -1466,6 +1498,15 @@ int32x2_t test_vcls_s32(int32x2_t a) {
return vcls_s32(a);
}
+// CHECK-LABEL: @test_vcls_u32(
+// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8>
+// CHECK: [[VCLS_V1_I:%.*]] = call <2 x i32> @llvm.aarch64.neon.cls.v2i32(<2 x i32> %a)
+// CHECK: [[VCLS_V2_I:%.*]] = bitcast <2 x i32> [[VCLS_V1_I]] to <8 x i8>
+// CHECK: ret <2 x i32> [[VCLS_V1_I]]
+int32x2_t test_vcls_u32(uint32x2_t a) {
+ return vcls_u32(a);
+}
+
// CHECK-LABEL: @test_vclsq_s32(
// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
// CHECK: [[VCLSQ_V1_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.cls.v4i32(<4 x i32> %a)
@@ -1475,6 +1516,15 @@ int32x4_t test_vclsq_s32(int32x4_t a) {
return vclsq_s32(a);
}
+// CHECK-LABEL: @test_vclsq_u32(
+// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
+// CHECK: [[VCLSQ_V1_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.cls.v4i32(<4 x i32> %a)
+// CHECK: [[VCLSQ_V2_I:%.*]] = bitcast <4 x i32> [[VCLSQ_V1_I]] to <16 x i8>
+// CHECK: ret <4 x i32> [[VCLSQ_V1_I]]
+int32x4_t test_vclsq_u32(uint32x4_t a) {
+ return vclsq_u32(a);
+}
+
// CHECK-LABEL: @test_vclz_s8(
// CHECK: [[VCLZ_V_I:%.*]] = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false)
// CHECK: ret <8 x i8> [[VCLZ_V_I]]
diff --git a/clang/test/CodeGen/arm_neon_intrinsics.c b/clang/test/CodeGen/arm_neon_intrinsics.c
index 56e105a41962..a84f75ad422e 100644
--- a/clang/test/CodeGen/arm_neon_intrinsics.c
+++ b/clang/test/CodeGen/arm_neon_intrinsics.c
@@ -1776,6 +1776,31 @@ int32x2_t test_vcls_s32(int32x2_t a) {
return vcls_s32(a);
}
+// CHECK-LABEL: @test_vcls_u8(
+// CHECK: [[VCLS_V_I:%.*]] = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %a)
+// CHECK: ret <8 x i8> [[VCLS_V_I]]
+int8x8_t test_vcls_u8(uint8x8_t a) {
+ return vcls_u8(a);
+}
+
+// CHECK-LABEL: @test_vcls_u16(
+// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
+// CHECK: [[VCLS_V1_I:%.*]] = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %a)
+// CHECK: [[VCLS_V2_I:%.*]] = bitcast <4 x i16> [[VCLS_V1_I]] to <8 x i8>
+// CHECK: ret <4 x i16> [[VCLS_V1_I]]
+int16x4_t test_vcls_u16(uint16x4_t a) {
+ return vcls_u16(a);
+}
+
+// CHECK-LABEL: @test_vcls_u32(
+// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8>
+// CHECK: [[VCLS_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %a)
+// CHECK: [[VCLS_V2_I:%.*]] = bitcast <2 x i32> [[VCLS_V1_I]] to <8 x i8>
+// CHECK: ret <2 x i32> [[VCLS_V1_I]]
+int32x2_t test_vcls_u32(uint32x2_t a) {
+ return vcls_u32(a);
+}
+
// CHECK-LABEL: @test_vclsq_s8(
// CHECK: [[VCLSQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %a)
// CHECK: ret <16 x i8> [[VCLSQ_V_I]]
@@ -1801,6 +1826,31 @@ int32x4_t test_vclsq_s32(int32x4_t a) {
return vclsq_s32(a);
}
+// CHECK-LABEL: @test_vclsq_u8(
+// CHECK: [[VCLSQ_V_I:%.*]] = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %a)
+// CHECK: ret <16 x i8> [[VCLSQ_V_I]]
+int8x16_t test_vclsq_u8(uint8x16_t a) {
+ return vclsq_u8(a);
+}
+
+// CHECK-LABEL: @test_vclsq_u16(
+// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
+// CHECK: [[VCLSQ_V1_I:%.*]] = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %a)
+// CHECK: [[VCLSQ_V2_I:%.*]] = bitcast <8 x i16> [[VCLSQ_V1_I]] to <16 x i8>
+// CHECK: ret <8 x i16> [[VCLSQ_V1_I]]
+int16x8_t test_vclsq_u16(uint16x8_t a) {
+ return vclsq_u16(a);
+}
+
+// CHECK-LABEL: @test_vclsq_u32(
+// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
+// CHECK: [[VCLSQ_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %a)
+// CHECK: [[VCLSQ_V2_I:%.*]] = bitcast <4 x i32> [[VCLSQ_V1_I]] to <16 x i8>
+// CHECK: ret <4 x i32> [[VCLSQ_V1_I]]
+int32x4_t test_vclsq_u32(uint32x4_t a) {
+ return vclsq_u32(a);
+}
+
// CHECK-LABEL: @test_vclt_s8(
// CHECK: [[CMP_I:%.*]] = icmp slt <8 x i8> %a, %b
// CHECK: [[SEXT_I:%.*]] = sext <8 x i1> [[CMP_I]] to <8 x i8>
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