[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


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Comment at: clang/include/clang/Basic/riscv_vector.td:66
+//      element type which is bool
+//   0: void type, ignores "t"
+//   z: size_t, ignores "t"
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jrtc27 wrote:
> khchen wrote:
> > jrtc27 wrote:
> > > Then why aren't these just base types? We don't have to follow the brain-dead nature of printf.
> > Basically builtin interface is instantiated by the "base type + LMUL" with type transformers. But in some intrinsic function we need a specific type regardless "base type + LMUL"
> > ex. `vuint32m2_t vssrl_vx_u32m2_vl (vuint32m2_t op1, uint8_t op2, size_t vl);`
> Then fix the way you define these? This is just bad design IMO.
For each signature there is effectively a single key type that is a vector. The type transformer is a list of rules for how to derive all of the other operands from that one key type. Conceptually similar to LLVMScalarOrSameVectorWidth or LLVMHalfElementsVectorType in Intrinsics.td. Some types are fixed and don't vary by the key type. Like the size_t vl operand or a store intrinsic returning void.  There is no separate place to put a base type.


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  https://reviews.llvm.org/D95016/new/

https://reviews.llvm.org/D95016