[PATCH] D97264: [RISCV] Define types for Zvlsseg.

[Hsiangkai Wang via Phabricator via cfe-commits]

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The types in Zvlsseg occupy multiple vector registers. We use Record type in clang to represent Zvlsseg types. It will not increase the number of builtin types in clang. It just adds multiple implicit defined Record types for Zvlsseg.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D97264

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/Basic/Builtins.def
  clang/include/clang/Basic/RISCVVTypes.def
  clang/lib/AST/ASTContext.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Sema/Sema.cpp
  clang/test/Sema/riscv-types.c

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