[PATCH] D97053: [clang][SVE] Don't warn on vector to sizeless builtin implicit conversion

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

Is this change specific to fixed vectors declared with arm_sve_vector_bits or any of the subclasses of VectorType? If it allows the others, how do we know for sure that there are enough bits in the scalable type for the fixed vector. I ask because RISCV is also using sizeless builtin types for our vectors as of D92715 <https://reviews.llvm.org/D92715>.


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  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97053/new/

https://reviews.llvm.org/D97053