[PATCH] D96906: [AMDGPU] gfx90a support

Stanislav Mekhanoshin via Phabricator via cfe-commits cfe-commits at lists.llvm.org
Wed Feb 17 16:02:37 PST 2021 

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa8d9d50762c4: [AMDGPU] gfx90a support (authored by rampitec).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Changed prior to commit:
  https://reviews.llvm.org/D96906?vs=324434&id=324456#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96906/new/

https://reviews.llvm.org/D96906

Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Basic/BuiltinsAMDGPU.def
  clang/include/clang/Basic/Cuda.h
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Cuda.cpp
  clang/lib/Basic/Targets/AMDGPU.cpp
  clang/lib/Basic/Targets/NVPTX.cpp
  clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
  clang/test/CodeGenOpenCL/amdgpu-features.cl
  clang/test/CodeGenOpenCL/builtins-amdgcn-mfma.cl
  clang/test/Driver/amdgpu-features.c
  clang/test/Driver/amdgpu-macros.cl
  clang/test/Driver/amdgpu-mcpu.cl
  clang/test/Driver/cuda-bad-arch.cu
  clang/test/Driver/hip-toolchain-features.hip
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/SemaOpenCL/builtins-amdgcn-error-gfx90a-param.cl
  llvm/docs/AMDGPUUsage.rst
  llvm/include/llvm/BinaryFormat/ELF.h
  llvm/include/llvm/IR/IntrinsicsAMDGPU.td
  llvm/include/llvm/Support/AMDHSAKernelDescriptor.h
  llvm/include/llvm/Support/TargetParser.h
  llvm/lib/Object/ELFObjectFile.cpp
  llvm/lib/ObjectYAML/ELFYAML.cpp
  llvm/lib/Support/TargetParser.cpp
  llvm/lib/Target/AMDGPU/AMDGPU.td
  llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h
  llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
  llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
  llvm/lib/Target/AMDGPU/AMDGPUGISel.td
  llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
  llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
  llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
  llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
  llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
  llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  llvm/lib/Target/AMDGPU/BUFInstructions.td
  llvm/lib/Target/AMDGPU/DSInstructions.td
  llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
  llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
  llvm/lib/Target/AMDGPU/FLATInstructions.td
  llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
  llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
  llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
  llvm/lib/Target/AMDGPU/GCNProcessors.td
  llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
  llvm/lib/Target/AMDGPU/GCNRegPressure.h
  llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
  llvm/lib/Target/AMDGPU/GCNSubtarget.h
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
  llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
  llvm/lib/Target/AMDGPU/MIMGInstructions.td
  llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp
  llvm/lib/Target/AMDGPU/SIDefines.h
  llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
  llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
  llvm/lib/Target/AMDGPU/SIInstrFormats.td
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/lib/Target/AMDGPU/SIInstrInfo.td
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
  llvm/lib/Target/AMDGPU/SIProgramInfo.h
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/lib/Target/AMDGPU/SISchedule.td
  llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
  llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
  llvm/lib/Target/AMDGPU/VOP1Instructions.td
  llvm/lib/Target/AMDGPU/VOP2Instructions.td
  llvm/lib/Target/AMDGPU/VOP3Instructions.td
  llvm/lib/Target/AMDGPU/VOP3PInstructions.td
  llvm/lib/Target/AMDGPU/VOPInstructions.td
  llvm/test/Analysis/CostModel/AMDGPU/fadd.ll
  llvm/test/Analysis/CostModel/AMDGPU/fma.ll
  llvm/test/Analysis/CostModel/AMDGPU/fmul.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.s96.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd-with-ret.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
  llvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir
  llvm/test/CodeGen/AMDGPU/acc-ldst.ll
  llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
  llvm/test/CodeGen/AMDGPU/adjust-writemask-vectorized.ll
  llvm/test/CodeGen/AMDGPU/agpr-csr.ll
  llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
  llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
  llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir
  llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir
  llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
  llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
  llvm/test/CodeGen/AMDGPU/bundle-latency.mir
  llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
  llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
  llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir
  llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
  llvm/test/CodeGen/AMDGPU/coalesce-vgpr-alignment.ll
  llvm/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir
  llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
  llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
  llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir
  llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
  llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
  llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir
  llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
  llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
  llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
  llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
  llvm/test/CodeGen/AMDGPU/dead-lane.mir
  llvm/test/CodeGen/AMDGPU/dead_copy.mir
  llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
  llvm/test/CodeGen/AMDGPU/dpp64_combine.ll
  llvm/test/CodeGen/AMDGPU/dpp64_combine.mir
  llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
  llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
  llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir
  llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
  llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir
  llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
  llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir
  llvm/test/CodeGen/AMDGPU/fma.f64.ll
  llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir
  llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
  llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
  llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
  llvm/test/CodeGen/AMDGPU/fold-multiple.mir
  llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
  llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
  llvm/test/CodeGen/AMDGPU/gfx90a-enc.ll
  llvm/test/CodeGen/AMDGPU/global-atomics-fp.ll
  llvm/test/CodeGen/AMDGPU/hard-clauses.mir
  llvm/test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
  llvm/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir
  llvm/test/CodeGen/AMDGPU/hazard-in-bundle.mir
  llvm/test/CodeGen/AMDGPU/hazard-inlineasm.mir
  llvm/test/CodeGen/AMDGPU/hazard-pass-ordering.mir
  llvm/test/CodeGen/AMDGPU/hazard-recognizer-meta-insts.mir
  llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
  llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
  llvm/test/CodeGen/AMDGPU/insert-skips-flat-vmem.mir
  llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir
  llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
  llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
  llvm/test/CodeGen/AMDGPU/lds-branch-vmem-hazard.mir
  llvm/test/CodeGen/AMDGPU/limit-coalesce.mir
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.fadd.gfx90a.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.fadd.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.gfx90a.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.i8.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
  llvm/test/CodeGen/AMDGPU/llvm.pow-gfx9.ll
  llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
  llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
  llvm/test/CodeGen/AMDGPU/mai-hazards.mir
  llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
  llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-addrspace.mir
  llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
  llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
  llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
  llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
  (109 more files...)

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