[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai added inline comments.


================
Comment at: clang/include/clang/Basic/riscv_vector.td:128
+  // after an underscore (_). It is instantiated like Prototype.
+  string MangledSuffix = managed_suffix;
+
----------------
mangled_suffix


================
Comment at: clang/include/clang/Basic/riscv_vector.td:147
+
+  // If HasMask, this flag states that this builtin has a merge operand. It is
+  // always the first operand.
----------------
"has a maskedoff operand"


================
Comment at: clang/include/clang/Basic/riscv_vector.td:149
+  // always the first operand.
+  bit HasMergeOperand = true;
+
----------------
Propose to use HasMaskedOffOperand.


================
Comment at: clang/include/clang/Basic/riscv_vector.td:161
+  // This builtin is valid for the given exponental LMULs.
+  list<int> ELMUL = [0, 1, 2, 3, -1, -2, -3];
+
----------------
EMUL according to specification.


================
Comment at: clang/include/clang/Basic/riscv_vector.td:191
+multiclass GenRVVBuiltin<string suffix, string prototype, string type_range,
+                 bit gen, string managed_suffix = ""> {
+ if !or(!eq(gen_all, true), !eq(gen, true))  then {
----------------
mangled_suffix


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95016/new/

https://reviews.llvm.org/D95016