[PATCH] D94779: [Clang] Ensure vector predication pragma is ignored only when vectorization width is 1.

[Malhar via Phabricator via cfe-commits]

malharJ added a comment.

I had a look at the Clang Language Extension <https://clang.llvm.org/docs/LanguageExtensions.html#extensions-for-loop-hint-optimizations> ... and I saw this:

> Specifying a width/count of 1 disables the optimization, and is equivalent to vectorize(disable) or interleave(disable).

And regarding the original condition,  it seems to check whether vector predication has been specified and  vectorization is not disabled explicitly.
I think at the very least we should have Attrs.VectorizeWidth > 1 since it is being ANDed ?

  if (Attrs.VectorizePredicateEnable != LoopAttributes::Unspecified &&
      Attrs.VectorizeEnable != LoopAttributes::Disable &&
       Attrs.VectorizeWidth < 1)

I put in

  && Attrs.VectorizeWidth != 1

since the Clang parser threw an error when passing a value of 0 for the width and I thought it would be good to indicate explicitly that we don't want equal to 1.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D94779/new/

https://reviews.llvm.org/D94779