[clang] 7d4a8bc - [AArch64] Add +flagm archictecture option, allowing the v8.4a flag modification extension.
Mark Murray via cfe-commits
cfe-commits at lists.llvm.org
Fri Jan 8 05:22:13 PST 2021
Author: Mark Murray
Date: 2021-01-08T13:21:12Z
New Revision: 7d4a8bc417bf75b5e4034674a4255173d0089e68
URL: https://github.com/llvm/llvm-project/commit/7d4a8bc417bf75b5e4034674a4255173d0089e68
DIFF: https://github.com/llvm/llvm-project/commit/7d4a8bc417bf75b5e4034674a4255173d0089e68.diff
LOG: [AArch64] Add +flagm archictecture option, allowing the v8.4a flag modification extension.
Differential Revision: https://reviews.llvm.org/D94081
Added:
Modified:
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/AArch64.h
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/lib/Support/AArch64TargetParser.cpp
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/test/MC/AArch64/armv8.4a-flag.s
llvm/unittests/Support/TargetParserTest.cpp
Removed:
################################################################################
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index d03bca9cfd90..312c822ebb05 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -520,6 +520,8 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasLSE = true;
if (Feature == "+ls64")
HasLS64 = true;
+ if (Feature == "+flagm")
+ HasFlagM = true;
}
setDataLayout();
diff --git a/clang/lib/Basic/Targets/AArch64.h b/clang/lib/Basic/Targets/AArch64.h
index 5f24ab6a4d61..2809fbce9c88 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -47,6 +47,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
bool HasMatmulFP64;
bool HasMatmulFP32;
bool HasLSE;
+ bool HasFlagM;
llvm::AArch64::ArchKind ArchKind;
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def b/llvm/include/llvm/Support/AArch64TargetParser.def
index 38cc2e753740..5f36b0eecff9 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.def
+++ b/llvm/include/llvm/Support/AArch64TargetParser.def
@@ -109,6 +109,7 @@ AARCH64_ARCH_EXT_NAME("tme", AArch64::AEK_TME, "+tme", "-tme"
AARCH64_ARCH_EXT_NAME("ls64", AArch64::AEK_LS64, "+ls64", "-ls64")
AARCH64_ARCH_EXT_NAME("brbe", AArch64::AEK_BRBE, "+brbe", "-brbe")
AARCH64_ARCH_EXT_NAME("pauth", AArch64::AEK_PAUTH, "+pauth", "-pauth")
+AARCH64_ARCH_EXT_NAME("flagm", AArch64::AEK_FLAGM, "+flagm", "-flagm")
#undef AARCH64_ARCH_EXT_NAME
#ifndef AARCH64_CPU_NAME
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.h b/llvm/include/llvm/Support/AArch64TargetParser.h
index 35827517d7fc..7c9e245e3889 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.h
+++ b/llvm/include/llvm/Support/AArch64TargetParser.h
@@ -65,6 +65,7 @@ enum ArchExtKind : uint64_t {
AEK_LS64 = 1ULL << 33,
AEK_BRBE = 1ULL << 34,
AEK_PAUTH = 1ULL << 35,
+ AEK_FLAGM = 1ULL << 36,
};
enum class ArchKind {
diff --git a/llvm/lib/Support/AArch64TargetParser.cpp b/llvm/lib/Support/AArch64TargetParser.cpp
index be595e83dbef..503a7bd49d15 100644
--- a/llvm/lib/Support/AArch64TargetParser.cpp
+++ b/llvm/lib/Support/AArch64TargetParser.cpp
@@ -104,6 +104,8 @@ bool AArch64::getExtensionFeatures(uint64_t Extensions,
Features.push_back("+brbe");
if (Extensions & AEK_PAUTH)
Features.push_back("+pauth");
+ if (Extensions & AEK_FLAGM)
+ Features.push_back("+flagm");
return true;
}
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 1f1bf0ac1657..002efd700cc2 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -316,8 +316,8 @@ def FeatureTLB_RMI : SubtargetFeature<
"tlb-rmi", "HasTLB_RMI", "true",
"Enable v8.4-A TLB Range and Maintenance Instructions">;
-def FeatureFMI : SubtargetFeature<
- "fmi", "HasFMI", "true",
+def FeatureFlagM : SubtargetFeature<
+ "flagm", "HasFlagM", "true",
"Enable v8.4-A Flag Manipulation Instructions">;
// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
@@ -445,7 +445,7 @@ def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
"Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
FeatureNV, FeatureMPAM, FeatureDIT,
FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeaturePMU, FeatureTLB_RMI,
- FeatureFMI, FeatureRCPC_IMMO]>;
+ FeatureFlagM, FeatureRCPC_IMMO]>;
def HasV8_5aOps : SubtargetFeature<
"v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
@@ -474,7 +474,7 @@ def HasV8_0rOps : SubtargetFeature<
FeaturePAuth, FeatureRCPC,
//v8.4
FeatureDotProd, FeatureFP16FML, FeatureTRACEV8_4,
- FeatureTLB_RMI, FeatureFMI, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO,
+ FeatureTLB_RMI, FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO,
//v8.5
FeatureSSBS, FeaturePredRes, FeatureSB, FeatureSpecRestrict]>;
@@ -697,7 +697,7 @@ def ProcA78C : SubtargetFeature<"cortex-a78c", "ARMProcFamily",
HasV8_2aOps,
FeatureCrypto,
FeatureDotProd,
- FeatureFMI,
+ FeatureFlagM,
FeatureFP16FML,
FeatureFPARMv8,
FeatureFullFP16,
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index f1fd849dc362..54eda1544437 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -69,8 +69,8 @@ def HasPMU : Predicate<"Subtarget->hasPMU()">,
def HasTLB_RMI : Predicate<"Subtarget->hasTLB_RMI()">,
AssemblerPredicate<(all_of FeatureTLB_RMI), "tlb-rmi">;
-def HasFMI : Predicate<"Subtarget->hasFMI()">,
- AssemblerPredicate<(all_of FeatureFMI), "fmi">;
+def HasFlagM : Predicate<"Subtarget->hasFlagM()">,
+ AssemblerPredicate<(all_of FeatureFlagM), "flagm">;
def HasRCPC_IMMO : Predicate<"Subtarget->hasRCPCImm()">,
AssemblerPredicate<(all_of FeatureRCPC_IMMO), "rcpc-immo">;
@@ -1149,7 +1149,7 @@ def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
} // HasJS, HasFPARMv8
// v8.4 Flag manipulation instructions
-let Predicates = [HasFMI], Defs = [NZCV], Uses = [NZCV] in {
+let Predicates = [HasFlagM], Defs = [NZCV], Uses = [NZCV] in {
def CFINV : SimpleSystemI<0, (ins), "cfinv", "">, Sched<[WriteSys]> {
let Inst{20-5} = 0b0000001000000000;
}
@@ -1157,7 +1157,7 @@ def SETF8 : BaseFlagManipulation<0, 0, (ins GPR32:$Rn), "setf8", "{\t$Rn}">;
def SETF16 : BaseFlagManipulation<0, 1, (ins GPR32:$Rn), "setf16", "{\t$Rn}">;
def RMIF : FlagRotate<(ins GPR64:$Rn, uimm6:$imm, imm0_15:$mask), "rmif",
"{\t$Rn, $imm, $mask}">;
-} // HasFMI
+} // HasFlagM
// v8.5 flag manipulation instructions
let Predicates = [HasAltNZCV], Uses = [NZCV], Defs = [NZCV] in {
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 66b4b303aa6b..a2abd609d49e 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -140,7 +140,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
bool HasSEL2 = false;
bool HasPMU = false;
bool HasTLB_RMI = false;
- bool HasFMI = false;
+ bool HasFlagM = false;
bool HasRCPC_IMMO = false;
bool HasLSLFast = false;
@@ -513,7 +513,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
bool hasSEL2() const { return HasSEL2; }
bool hasPMU() const { return HasPMU; }
bool hasTLB_RMI() const { return HasTLB_RMI; }
- bool hasFMI() const { return HasFMI; }
+ bool hasFlagM() const { return HasFlagM; }
bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
bool addrSinkUsingGEPs() const override {
diff --git a/llvm/test/MC/AArch64/armv8.4a-flag.s b/llvm/test/MC/AArch64/armv8.4a-flag.s
index 154ed425bb60..7f73c4278ca9 100644
--- a/llvm/test/MC/AArch64/armv8.4a-flag.s
+++ b/llvm/test/MC/AArch64/armv8.4a-flag.s
@@ -1,13 +1,13 @@
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a %s -o - | \
// RUN: FileCheck %s
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+fmi %s -o - 2>&1 | \
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+flagm %s -o - 2>&1 | \
// RUN: FileCheck %s
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a %s -o - 2>&1 | \
// RUN: FileCheck %s --check-prefix=ERROR
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,-fmi %s -o - 2>&1 | \
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,-flagm %s -o - 2>&1 | \
// RUN: FileCheck %s --check-prefix=ERROR
//------------------------------------------------------------------------------
@@ -30,24 +30,24 @@
//CHECK-NEXT: rmif x1, #63, #15 // encoding: [0x2f,0x84,0x1f,0xba]
//CHECK-NEXT: rmif xzr, #63, #15 // encoding: [0xef,0x87,0x1f,0xba]
-//ERROR: error: instruction requires: fmi
+//ERROR: error: instruction requires: flagm
//ERROR-NEXT: cfinv
//ERROR-NEXT: ^
-//ERROR-NEXT: error: instruction requires: fmi
+//ERROR-NEXT: error: instruction requires: flagm
//ERROR-NEXT: setf8 w1
//ERROR-NEXT: ^
-//ERROR-NEXT: error: instruction requires: fmi
+//ERROR-NEXT: error: instruction requires: flagm
//ERROR-NEXT: setf8 wzr
//ERROR-NEXT: ^
-//ERROR-NEXT: error: instruction requires: fmi
+//ERROR-NEXT: error: instruction requires: flagm
//ERROR-NEXT: setf16 w1
//ERROR-NEXT: ^
-//ERROR-NEXT: error: instruction requires: fmi
+//ERROR-NEXT: error: instruction requires: flagm
//ERROR-NEXT: setf16 wzr
//ERROR-NEXT: ^
-//ERROR-NEXT: error: instruction requires: fmi
+//ERROR-NEXT: error: instruction requires: flagm
//ERROR-NEXT: rmif x1, #63, #15
//ERROR-NEXT: ^
-//ERROR-NEXT: error: instruction requires: fmi
+//ERROR-NEXT: error: instruction requires: flagm
//ERROR-NEXT: rmif xzr, #63, #15
//ERROR-NEXT: ^
diff --git a/llvm/unittests/Support/TargetParserTest.cpp b/llvm/unittests/Support/TargetParserTest.cpp
index 349263d7af43..a0c36f1ad6f1 100644
--- a/llvm/unittests/Support/TargetParserTest.cpp
+++ b/llvm/unittests/Support/TargetParserTest.cpp
@@ -1408,6 +1408,7 @@ TEST(TargetParserTest, AArch64ArchFeatures) {
TEST(TargetParserTest, AArch64ArchExtFeature) {
const char *ArchExt[][4] = {{"crc", "nocrc", "+crc", "-crc"},
{"crypto", "nocrypto", "+crypto", "-crypto"},
+ {"flagm", "noflagm", "+flagm", "-flagm"},
{"fp", "nofp", "+fp-armv8", "-fp-armv8"},
{"simd", "nosimd", "+neon", "-neon"},
{"fp16", "nofp16", "+fullfp16", "-fullfp16"},
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