[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

I think it would be possible to add a new attribute to define these types. But only specific values for parameters would be allowed so that it could only generate the exact types we see here and the future segment load patches. It wouldn't be general purpose like vector_size since the backend design has a contract about how to translate the LMUL value from the scalable type.

This would introduce a new type in the AST or at least new subtype of VectorType. This new type would need to be checked for in multiple places in the compiler to define its behavior. As a datapoint VectorType::SveFixedLengthDataVector appears 20 times. It's not clear that's a reduction in complexity versus following what was already done with AArch64SVEACLETypes.def. But I'm not a frontend expert.


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  https://reviews.llvm.org/D92715/new/

https://reviews.llvm.org/D92715