[PATCH] D91596: [PowerPC] [Clang] Fix alignment of 128-bit floating types

[Qiu Chaofan via Phabricator via cfe-commits]

qiucf created this revision.
qiucf added reviewers: jsji, nemanjai, uweigand, PowerPC, steven.zhang, rjmccall.
Herald added subscribers: cfe-commits, shchenz, kbarton.
Herald added a project: clang.
qiucf requested review of this revision.

According to ELF v2 ABI, both IEEE 128-bit and IBM extended floating point variables should be quad-word (16 bytes) aligned. Previously, only vector types are considered aligned as quad-word on Power.

Without this fix, IEEE 128-bit fp will be passed incorrectly in va_arg cases.

(the patch is not patchable since I generated it for easier review, the case is a new file)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91596

Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/ppc64le-varargs-f128.c


Index: clang/test/CodeGen/ppc64le-varargs-f128.c
===================================================================
--- clang/test/CodeGen/ppc64le-varargs-f128.c
+++ clang/test/CodeGen/ppc64le-varargs-f128.c
@@ -9,8 +9,11 @@
 
 // IEEE-LABEL: define fp128 @f128(i32 signext %n, ...)
 // IEEE: call void @llvm.va_start(i8* %{{[0-9a-zA-Z_.]+}})
-// IEEE: %[[P4:[0-9a-zA-Z_.]+]] = bitcast i8* %{{[0-9a-zA-Z_.]+}} to fp128*
-// IEEE: %{{[0-9a-zA-Z_.]+}} = load fp128, fp128* %[[P4]], align 8
+// IEEE: %[[P1:[0-9a-zA-Z_.]+]] = add i64 %{{[0-9a-zA-Z_.]+}}, 15
+// IEEE: %[[P2:[0-9a-zA-Z_.]+]] = and i64 %[[P1]], -16
+// IEEE: %[[P3:[0-9a-zA-Z_.]+]] = inttoptr i64 %[[P2]] to i8*
+// IEEE: %[[P4:[0-9a-zA-Z_.]+]] = bitcast i8* %[[P3]] to fp128*
+// IEEE: %{{[0-9a-zA-Z_.]+}} = load fp128, fp128* %[[P4]], align 16
 // IEEE: call void @llvm.va_end(i8* %{{[0-9a-zA-Z_.]+}})
 __float128 f128(int n, ...) {
   va_list ap;
@@ -22,14 +25,20 @@
 
 // IEEE-LABEL: define fp128 @long_double(i32 signext %n, ...)
 // IEEE: call void @llvm.va_start(i8* %{{[0-9a-zA-Z_.]+}})
-// IEEE: %[[P4:[0-9a-zA-Z_.]+]] = bitcast i8* %{{[0-9a-zA-Z_.]+}} to fp128*
-// IEEE: %{{[0-9a-zA-Z_.]+}} = load fp128, fp128* %[[P4]], align 8
+// IEEE: %[[P1:[0-9a-zA-Z_.]+]] = add i64 %{{[0-9a-zA-Z_.]+}}, 15
+// IEEE: %[[P2:[0-9a-zA-Z_.]+]] = and i64 %[[P1]], -16
+// IEEE: %[[P3:[0-9a-zA-Z_.]+]] = inttoptr i64 %[[P2]] to i8*
+// IEEE: %[[P4:[0-9a-zA-Z_.]+]] = bitcast i8* %[[P3]] to fp128*
+// IEEE: %{{[0-9a-zA-Z_.]+}} = load fp128, fp128* %[[P4]], align 16
 // IEEE: call void @llvm.va_end(i8* %{{[0-9a-zA-Z_.]+}})
 
 // IBM-LABEL: define ppc_fp128 @long_double(i32 signext %n, ...)
 // IBM: call void @llvm.va_start(i8* %{{[0-9a-zA-Z_.]+}})
-// IBM: %[[P4:[0-9a-zA-Z_.]+]] = bitcast i8* %{{[0-9a-zA-Z_.]+}} to ppc_fp128*
-// IBM: %{{[0-9a-zA-Z_.]+}} = load ppc_fp128, ppc_fp128* %[[P4]], align 8
+// IBM: %[[P1:[0-9a-zA-Z_.]+]] = add i64 %{{[0-9a-zA-Z_.]+}}, 15
+// IBM: %[[P2:[0-9a-zA-Z_.]+]] = and i64 %[[P1]], -16
+// IBM: %[[P3:[0-9a-zA-Z_.]+]] = inttoptr i64 %[[P2]] to i8*
+// IBM: %[[P4:[0-9a-zA-Z_.]+]] = bitcast i8* %[[P3]] to ppc_fp128*
+// IBM: %{{[0-9a-zA-Z_.]+}} = load ppc_fp128, ppc_fp128* %[[P4]], align 16
 // IBM: call void @llvm.va_end(i8* %{{[0-9a-zA-Z_.]+}})
 long double long_double(int n, ...) {
   va_list ap;
Index: clang/lib/CodeGen/TargetInfo.cpp
===================================================================
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -5049,7 +5049,10 @@
       return CharUnits::fromQuantity(32);
 
     return CharUnits::fromQuantity(16);
-  } else if (Ty->isVectorType()) {
+  } else if (Ty->isVectorType() || Ty->isRealFloatingType()) {
+    // IEEE 128-bit floating numbers are also stored in vector registers.
+    // And both IEEE quad-precision and IBM extended double (ppc_fp128) should
+    // be quad-word aligned.
     return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);
   }
 


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