[PATCH] D91279: [PowerPC] DForm instructions should be preferred when using zero register

[Amy Kwan via Phabricator via cfe-commits]

amyk added a comment.

Please also address the clang-format comment.



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Comment at: llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp:417
+
+          // should prefer D-form if LXVX / STXVX uses a ZERO or ZERO8
+          if (MI.getOpcode() == PPC::LXVX || MI.getOpcode() == PPC::STXVX) {
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Please capitalize and end with a period for the comments. 
Is it possible to elaborate a bit more on the comments? In terms of why we were prefer the D-Forms, and why we should not apply the transformation if its a frame index. 


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Comment at: llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll:2
 ; RUN: llc < %s -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
-; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ 
 ; RUN:   | FileCheck %s --check-prefix=CHECK-P8
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I think this is an unrelated change. 


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D91279/new/

https://reviews.llvm.org/D91279