[PATCH] D91251: [VE] Support vector register in inline asm

[Kazushi Marukawa via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG6e0ae20f3b98: [VE] Support vector register in inline asm (authored by kaz7).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91251/new/

https://reviews.llvm.org/D91251

Files:
  clang/lib/Basic/Targets/VE.h
  clang/test/CodeGen/VE/ve-inline-asm.c


Index: clang/test/CodeGen/VE/ve-inline-asm.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/VE/ve-inline-asm.c
@@ -0,0 +1,23 @@
+// REQUIRES: ve-registered-target
+// RUN: %clang_cc1 -triple ve-linux-gnu -emit-llvm -o - %s | FileCheck %s
+
+void r(long v) {
+  long b;
+  asm("lea %0, 256(%1)"
+      : "=r"(b)
+      : "r"(v));
+  // CHECK: %1 = call i64 asm "lea $0, 256($1)", "=r,r"(i64 %0)
+}
+
+void v(char *ptr, char *ptr2) {
+  typedef double __vr __attribute__((__vector_size__(2048)));
+  __vr a;
+  asm("vld %0, 8, %1"
+      : "=v"(a)
+      : "r"(ptr));
+  asm("vst %0, 8, %1"
+      :
+      : "v"(a), "r"(ptr2));
+  // CHECK: %1 = call <256 x double> asm "vld $0, 8, $1", "=v,r"(i8* %0)
+  // CHECK: call void asm sideeffect "vst $0, 8, $1", "v,r"(<256 x double> %2, i8* %3)
+}
Index: clang/lib/Basic/Targets/VE.h
===================================================================
--- clang/lib/Basic/Targets/VE.h
+++ clang/lib/Basic/Targets/VE.h
@@ -160,6 +160,13 @@
 
   bool validateAsmConstraint(const char *&Name,
                              TargetInfo::ConstraintInfo &Info) const override {
+    switch (*Name) {
+    default:
+      return false;
+    case 'v':
+      Info.setAllowsRegister();
+      return true;
+    }
     return false;
   }
 


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