[PATCH] D89972: Add pipeline model for HiSilicon's TSV110

[Elvina Yakubova via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG93b99728b167: [AArch64] Add pipeline model for HiSilicon's TSV110 (authored by Elvina).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89972/new/

https://reviews.llvm.org/D89972

Files:
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64SchedTSV110.td
  llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
  llvm/test/CodeGen/AArch64/preferred-function-alignment.ll

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