[PATCH] D72218: [clang-tidy] new altera kernel name restriction check

[Aaron Ballman via Phabricator via cfe-commits]

aaron.ballman added inline comments.


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Comment at: clang-tools-extra/clang-tidy/altera/KernelNameRestrictionCheck.cpp:90
+    Check.diag(SM.getLocForStartOfFile(SM.getMainFileID()),
+               "Naming your OpenCL kernel source file 'kernel.cl', 'Verilog.cl'"
+               ", or 'VHDL.cl' could cause compilation errors.");
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aaron.ballman wrote:
> Similar here, I would word it something like: `compiling a source file named '%0' may result in additional compilation errors due to the name of the file; consider renaming the source file`
The diagnostic here doesn't look quite right. This is the case where the source compiland is named poorly, but the diagnostic is talking about including files. It looks like there's test coverage missing for this.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72218/new/

https://reviews.llvm.org/D72218