[clang] 700e632 - [Sema] Support Comma operator for fp16 vectors.
Florian Hahn via cfe-commits
cfe-commits at lists.llvm.org
Wed Sep 30 10:23:36 PDT 2020
Author: Alexandre Rames
Date: 2020-09-30T18:23:09+01:00
New Revision: 700e63293eea4a23440f300b1e9125ca2e80c6e9
URL: https://github.com/llvm/llvm-project/commit/700e63293eea4a23440f300b1e9125ca2e80c6e9
DIFF: https://github.com/llvm/llvm-project/commit/700e63293eea4a23440f300b1e9125ca2e80c6e9.diff
LOG: [Sema] Support Comma operator for fp16 vectors.
The current half vector was enforcing an assert expecting
"(LHS is half vector) == (RHS is half vector)"
for comma.
Reviewed By: ahatanak, fhahn
Differential Revision: https://reviews.llvm.org/D88265
Added:
Modified:
clang/lib/Sema/SemaExpr.cpp
clang/test/Sema/fp16vec-sema.c
Removed:
################################################################################
diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp
index a7c076657fb5..22840dd3dfe3 100644
--- a/clang/lib/Sema/SemaExpr.cpp
+++ b/clang/lib/Sema/SemaExpr.cpp
@@ -13940,9 +13940,10 @@ ExprResult Sema::CreateBuiltinBinOp(SourceLocation OpLoc,
// float vectors and truncating the result back to half vector. For now, we do
// this only when HalfArgsAndReturn is set (that is, when the target is arm or
// arm64).
- assert(isVector(RHS.get()->getType(), Context.HalfTy) ==
- isVector(LHS.get()->getType(), Context.HalfTy) &&
- "both sides are half vectors or neither sides are");
+ assert(
+ (Opc == BO_Comma || isVector(RHS.get()->getType(), Context.HalfTy) ==
+ isVector(LHS.get()->getType(), Context.HalfTy)) &&
+ "both sides are half vectors or neither sides are");
ConvertHalfVec =
needsConversionOfHalfVec(ConvertHalfVec, Context, LHS.get(), RHS.get());
diff --git a/clang/test/Sema/fp16vec-sema.c b/clang/test/Sema/fp16vec-sema.c
index aefb5f86a14b..f61ad4c91e89 100644
--- a/clang/test/Sema/fp16vec-sema.c
+++ b/clang/test/Sema/fp16vec-sema.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -fsyntax-only -verify %s
+// RUN: %clang_cc1 -fsyntax-only -Wno-unused-value -verify %s
typedef __fp16 half4 __attribute__ ((vector_size (8)));
typedef float float4 __attribute__ ((vector_size (16)));
@@ -28,6 +28,8 @@ void testFP16Vec(int c) {
sv0 = hv0 >= hv1;
sv0 = hv0 || hv1; // expected-error{{logical expression with vector types 'half4' (vector of 4 '__fp16' values) and 'half4' is only supported in C++}}
sv0 = hv0 && hv1; // expected-error{{logical expression with vector types 'half4' (vector of 4 '__fp16' values) and 'half4' is only supported in C++}}
+ hv0, 1;
+ 1, hv0;
// Implicit conversion between half vectors and float vectors are not allowed.
hv0 = fv0; // expected-error{{assigning to}}
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