[clang] 288c577 - [X86] Use inlineasm flag output for the _bittest* intrinsics.

Craig Topper via cfe-commits cfe-commits at lists.llvm.org
Mon Sep 28 13:34:25 PDT 2020


Author: Craig Topper
Date: 2020-09-28T13:33:22-07:00
New Revision: 288c5776c9d3cb14abe1c86f961c8ff166772d28

URL: https://github.com/llvm/llvm-project/commit/288c5776c9d3cb14abe1c86f961c8ff166772d28
DIFF: https://github.com/llvm/llvm-project/commit/288c5776c9d3cb14abe1c86f961c8ff166772d28.diff

LOG: [X86] Use inlineasm flag output for the _bittest* intrinsics.

Instead of expliciting emitting a setc in the inline asm instructions,
we can use flag output. This allows the backend to use the flag
directly if it is needed by a branch. Previously we needed a test
instruction to convert the register back to a flag.

If the flag can't be used directly, the backend will emit a setcc.

Differential Revision: https://reviews.llvm.org/D87888

Added: 
    llvm/test/CodeGen/X86/bittest-intrin.ll

Modified: 
    clang/lib/CodeGen/CGBuiltin.cpp
    clang/test/CodeGen/bittest-intrin.c

Removed: 
    


################################################################################
diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 102b5aefe8ff..57804494d9a5 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -805,10 +805,10 @@ static llvm::Value *EmitX86BitTestIntrinsic(CodeGenFunction &CGF,
   AsmOS << "bt";
   if (Action)
     AsmOS << Action;
-  AsmOS << SizeSuffix << " $2, ($1)\n\tsetc ${0:b}";
+  AsmOS << SizeSuffix << " $2, ($1)";
 
   // Build the constraints. FIXME: We should support immediates when possible.
-  std::string Constraints = "=r,r,r,~{cc},~{memory}";
+  std::string Constraints = "={@ccc},r,r,~{cc},~{memory}";
   std::string MachineClobbers = CGF.getTarget().getClobbers();
   if (!MachineClobbers.empty()) {
     Constraints += ',';

diff  --git a/clang/test/CodeGen/bittest-intrin.c b/clang/test/CodeGen/bittest-intrin.c
index ddc2af5454d7..25e367384d78 100644
--- a/clang/test/CodeGen/bittest-intrin.c
+++ b/clang/test/CodeGen/bittest-intrin.c
@@ -34,20 +34,20 @@ void test_arm(long *base, long idx) {
 #endif
 
 // X64-LABEL: define dso_local void @test32(i32* %base, i32 %idx)
-// X64: call i8 asm sideeffect "btl $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
-// X64: call i8 asm sideeffect "btcl $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
-// X64: call i8 asm sideeffect "btrl $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
-// X64: call i8 asm sideeffect "btsl $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
-// X64: call i8 asm sideeffect "lock btrl $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
-// X64: call i8 asm sideeffect "lock btsl $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
+// X64: call i8 asm sideeffect "btl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
+// X64: call i8 asm sideeffect "btcl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
+// X64: call i8 asm sideeffect "btrl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
+// X64: call i8 asm sideeffect "btsl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
+// X64: call i8 asm sideeffect "lock btrl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
+// X64: call i8 asm sideeffect "lock btsl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
 
 // X64-LABEL: define dso_local void @test64(i64* %base, i64 %idx)
-// X64: call i8 asm sideeffect "btq $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
-// X64: call i8 asm sideeffect "btcq $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
-// X64: call i8 asm sideeffect "btrq $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
-// X64: call i8 asm sideeffect "btsq $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
-// X64: call i8 asm sideeffect "lock btrq $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
-// X64: call i8 asm sideeffect "lock btsq $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
+// X64: call i8 asm sideeffect "btq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
+// X64: call i8 asm sideeffect "btcq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
+// X64: call i8 asm sideeffect "btrq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
+// X64: call i8 asm sideeffect "btsq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
+// X64: call i8 asm sideeffect "lock btrq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
+// X64: call i8 asm sideeffect "lock btsq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
 
 // ARM-LABEL: define dso_local {{.*}}void @test32(i32* %base, i32 %idx)
 // ARM: %[[IDXHI:[^ ]*]] = ashr i32 %{{.*}}, 3

diff  --git a/llvm/test/CodeGen/X86/bittest-intrin.ll b/llvm/test/CodeGen/X86/bittest-intrin.ll
new file mode 100644
index 000000000000..4ccd7d6a2c48
--- /dev/null
+++ b/llvm/test/CodeGen/X86/bittest-intrin.ll
@@ -0,0 +1,101 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-windows-msvc19.11.0 | FileCheck %s
+
+; This matches the code produced by clang/lib/CodeGen/bittest-intrin.c
+
+ at sink = global i8 0, align 1
+
+define void @test32(i32* %base, i32 %idx) {
+; CHECK-LABEL: test32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    btl %edx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    btcl %edx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    btrl %edx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    btsl %edx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    lock btrl %edx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    lock btsl %edx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    lock btsl %edx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    retq
+entry:
+  %0 = tail call i8 asm sideeffect "btl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx)
+  store volatile i8 %0, i8* @sink, align 1
+  %1 = tail call i8 asm sideeffect "btcl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx)
+  store volatile i8 %1, i8* @sink, align 1
+  %2 = tail call i8 asm sideeffect "btrl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx)
+  store volatile i8 %2, i8* @sink, align 1
+  %3 = tail call i8 asm sideeffect "btsl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx)
+  store volatile i8 %3, i8* @sink, align 1
+  %4 = tail call i8 asm sideeffect "lock btrl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx)
+  store volatile i8 %4, i8* @sink, align 1
+  %5 = tail call i8 asm sideeffect "lock btsl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx)
+  store volatile i8 %5, i8* @sink, align 1
+  %6 = tail call i8 asm sideeffect "lock btsl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx)
+  store volatile i8 %6, i8* @sink, align 1
+  ret void
+}
+
+; Function Attrs: nounwind uwtable
+define void @test64(i64* %base, i64 %idx) {
+; CHECK-LABEL: test64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    btq %rdx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    btcq %rdx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    btrq %rdx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    btsq %rdx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    lock btrq %rdx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    lock btsq %rdx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    retq
+entry:
+  %0 = tail call i8 asm sideeffect "btq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %base, i64 %idx)
+  store volatile i8 %0, i8* @sink, align 1
+  %1 = tail call i8 asm sideeffect "btcq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %base, i64 %idx)
+  store volatile i8 %1, i8* @sink, align 1
+  %2 = tail call i8 asm sideeffect "btrq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %base, i64 %idx)
+  store volatile i8 %2, i8* @sink, align 1
+  %3 = tail call i8 asm sideeffect "btsq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %base, i64 %idx)
+  store volatile i8 %3, i8* @sink, align 1
+  %4 = tail call i8 asm sideeffect "lock btrq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %base, i64 %idx)
+  store volatile i8 %4, i8* @sink, align 1
+  %5 = tail call i8 asm sideeffect "lock btsq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %base, i64 %idx)
+  store volatile i8 %5, i8* @sink, align 1
+  ret void
+}


        


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