[PATCH] D88265: Fix comma with half vectors.

[Florian Hahn via Phabricator via cfe-commits]

fhahn added inline comments.


================
Comment at: clang/lib/Sema/SemaExpr.cpp:13936
   // arm64).
-  assert(isVector(RHS.get()->getType(), Context.HalfTy) ==
-         isVector(LHS.get()->getType(), Context.HalfTy) &&
-         "both sides are half vectors or neither sides are");
+  assert(Opc == BO_Comma ||
+         isVector(RHS.get()->getType(), Context.HalfTy) ==
----------------
I think you need braces around the expression before `&& "..."`, otherwise some compilers may complain.


================
Comment at: clang/test/Sema/fp16vec-sema.c:29
   sv0 = hv0 >= hv1;
+  hv0, 1; // expected-warning 2 {{expression result unused}}
   sv0 = hv0 || hv1; // expected-error{{logical expression with vector types 'half4' (vector of 4 '__fp16' values) and 'half4' is only supported in C++}}
----------------
nit: it might be slightly better to move it 2 lines further down, so all operators that assign the result are grouped together. Also, should we add `1, hv0` as well?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88265/new/

https://reviews.llvm.org/D88265