[PATCH] D88233: [clang][aarch64] Address various fixed-length SVE vector operations

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, efriedma, rsandifo-arm.
Herald added subscribers: kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: clang.
c-rhodes requested review of this revision.

This patch adds tests and support for operations on SVE vectors created
by the 'arm_sve_vector_bits' attribute, described by the Arm C Language
Extensions (ACLE, version 00bet5, section 3.7.3.3) for SVE [1].

This covers the following:

- VLSTs support the same forms of element-wise initialization as GNU vectors.
- VLSTs support the same built-in C and C++ operators as GNU vectors.
- Conditional and binary expressions containing GNU and SVE vectors (fixed or sizeless) are invalid since the ambiguity around the result type affects the ABI.

No functional changes were required to support vector initialization and
operators. The functional changes are to address unsupported conditional and
binary expressions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D88233

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/AST/ASTContext.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/Sema/attr-arm-sve-vector-bits.c

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