[PATCH] D86819: [PowerPC][Power10] Implementation of 128-bit Binary Vector Rotate builtins

[Amy Kwan via Phabricator via cfe-commits]

amyk added inline comments.


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Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:4
 // RUN:   -target-cpu pwr10 -triple powerpc64-unknown-unknown -emit-llvm %s \
-// RUN:   -o - | FileCheck %s -check-prefixes=CHECK-BE,CHECK
+// RUN:   -o - | FileCheck %s -check-prefixes=CHECK-BE,CHECK -check-prefix=CHECK-COMMON
 // RUN: %clang_cc1 -target-feature +vsx \
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The `CHECK-COMMON` should not be needed. You can just use the `CHECK` prefix in the tests since we have set up check prefixes.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:1295
   def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>;
+  def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>;
+  def VRLQNM : VX1_VT5_VA5_VB5<325, "vrlqnm",
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If possible, I think it is better to leave the instruction patterns in the position they were in, and just add the patterns to them. 


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Comment at: llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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Please also add the BE run line. 


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D86819/new/

https://reviews.llvm.org/D86819