[PATCH] D87394: [PowerPC][Power10] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins

[Amy Kwan via Phabricator via cfe-commits]

amyk requested changes to this revision.
amyk added a comment.
This revision now requires changes to proceed.

A question I have is, is it possible for the 128-bit vector modulo instructions be open coded?



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Comment at: clang/lib/Headers/altivec.h:17394
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_mod(vector signed __int128 __a, vector signed __int128 __b) {
+  return __builtin_altivec_vmodsq(__a, __b);
----------------
nit: Move these under the existing `vec_mod` builtins.
Also, is it possible for these to be open coded instead? We have `vec_mod` for other types that are open coded. 



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Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:1300
+                               [(set v1i128:$vD, (int_ppc_altivec_vmodsq v1i128:$vA,
+                               v1i128:$vB))]>;
   def VMODUQ : VXForm_1<1547, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
----------------
nit: Indent `v1i128` underneath the top `v1i128`.


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  https://reviews.llvm.org/D87394/new/

https://reviews.llvm.org/D87394