[PATCH] D85743: [CodeGen][AArch64] Support arm_sve_vector_bits attribute

[Leonard Chan via Phabricator via cfe-commits]

leonardchan added a comment.

Hi! The `attr-arm-sve-vector-bits-call.c` test seems to be failing on our clang builders:

  FAIL: Clang :: CodeGen/attr-arm-sve-vector-bits-call.c (3020 of 25924)
  ******************** TEST 'Clang :: CodeGen/attr-arm-sve-vector-bits-call.c' FAILED ********************
  Script:
  --
  : 'RUN: at line 3';   /b/s/w/ir/k/staging/llvm_build/bin/clang -cc1 -internal-isystem /b/s/w/ir/k/staging/llvm_build/lib/clang/12.0.0/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -fallow-half-arguments-and-returns -S -O1 -emit-llvm -o - /b/s/w/ir/k/llvm-project/clang/test/CodeGen/attr-arm-sve-vector-bits-call.c | /b/s/w/ir/k/staging/llvm_build/bin/FileCheck /b/s/w/ir/k/llvm-project/clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  --
  Exit Code: 1
  
  Command Output (stderr):
  --
  warning: Compiler has made implicit assumption that TypeSize is not scalable. This may or may not lead to broken code.
  warning: Compiler has made implicit assumption that TypeSize is not scalable. This may or may not lead to broken code.
  /b/s/w/ir/k/llvm-project/clang/test/CodeGen/attr-arm-sve-vector-bits-call.c:67:16: error: CHECK-NEXT: is not on the line after the previous match
  // CHECK-NEXT: [[X_ADDR:%.*]] = alloca <vscale x 4 x i32>, align 16
                 ^
  <stdin>:52:2: note: 'next' match was here
   %retval.coerce.i = alloca <vscale x 4 x i32>, align 16
   ^
  <stdin>:50:7: note: previous match ended here
  entry:
        ^
  <stdin>:51:1: note: non-matching line after previous match is here
   %x.i = alloca <16 x i32>, align 16
  ^
  
  Input file: <stdin>
  Check file: /b/s/w/ir/k/llvm-project/clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  
  -dump-input=help explains the following input dump.
  
  Input was:
  <<<<<<
           .
           .
           .
          47: 
          48: ; Function Attrs: nounwind readnone
          49: define <vscale x 4 x i32> @sizeless_caller(<vscale x 4 x i32> %x) local_unnamed_addr #1 {
          50: entry:
          51:  %x.i = alloca <16 x i32>, align 16
          52:  %retval.coerce.i = alloca <vscale x 4 x i32>, align 16
  next:67      !~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ error: match on wrong line
          53:  %x.addr = alloca <vscale x 4 x i32>, align 16
          54:  %coerce.coerce = alloca <vscale x 4 x i32>, align 16
          55:  %coerce1 = alloca <16 x i32>, align 16
          56:  %saved-call-rvalue = alloca <16 x i32>, align 64
          57:  store <vscale x 4 x i32> %x, <vscale x 4 x i32>* %x.addr, align 16, !tbaa !5
           .
           .
           .
  >>>>>>
  
  --
  
  ********************
  Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.. 
  ********************
  Failed Tests (1):
    Clang :: CodeGen/attr-arm-sve-vector-bits-call.c

Could you take a look? Thanks.

Builder: https://luci-milo.appspot.com/p/fuchsia/builders/ci/clang-linux-x64/b8870800848452818112?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85743/new/

https://reviews.llvm.org/D85743