[PATCH] D85743: [CodeGen][AArch64] Support arm_sve_vector_bits attribute

[David Sherwood via Phabricator via cfe-commits]

david-arm added inline comments.


================
Comment at: clang/lib/CodeGen/CGCall.cpp:1342
+  if (SrcSize.getKnownMinSize() <= DstSize.getKnownMinSize() ||
+      (isa<llvm::ScalableVectorType>(SrcTy) ||
+       isa<llvm::ScalableVectorType>(DstTy))) {
----------------
I think if you restructure the code here you could do:

if (isa<llvm::ScalableVectorType>(SrcTy) || isa<llvm::ScalableVectorType>(DstTy) ||
    SrcSize.getFixedSize() <= DstSize.getFixedSize())

since you know that the scalable types have been eliminated by the time we do the "<=" comparison.



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Comment at: clang/lib/CodeGen/CGCall.cpp:1361
+        Tmp.getAlignment().getAsAlign(),
+        llvm::ConstantInt::get(CGF.IntPtrTy, DstSize.getKnownMinSize()));
   }
----------------
c-rhodes wrote:
> @efriedma If we're happy with the element bitcast above this can also be fixed but I wasn't if that was ok, although it's pretty much what was implemented in the original codegen patch.
Given the if statement above has eliminated scalable vector types I think it's safe to use DstSize.getFixedSize() here.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85743/new/

https://reviews.llvm.org/D85743