[PATCH] D85743: [CodeGen][AArch64] Support arm_sve_vector_bits attribute

[Eli Friedman via Phabricator via cfe-commits]

efriedma added inline comments.


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Comment at: clang/lib/AST/ItaniumMangle.cpp:3330
+// appendices to the Procedure Call Standard for the Arm Architecture, see:
+// https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#appendix-c-mangling
+void CXXNameMangler::mangleAArch64FixedSveVectorType(const VectorType *T) {
----------------
Mangling them the same way is going to cause practical issues; they're different types from a C++ perspective, so they need distinct manglings.  For example, you'll crash the compiler if you refer to both foo<svint64_t> and foo<fixed_int64_t>.


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Comment at: clang/lib/CodeGen/CGCall.cpp:1238
+    Src = EnterStructPointerForCoercedAccess(Src, SrcSTy,
+                                             DstSize.getKnownMinSize(), CGF);
     SrcTy = Src.getElementType();
----------------
getFixedSize()?


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Comment at: clang/lib/CodeGen/CGCall.cpp:1254
+  if ((!SrcSize.isScalable() && !DstSize.isScalable()) &&
+      SrcSize.getKnownMinSize() >= DstSize.getKnownMinSize()) {
     // Generally SrcSize is never greater than DstSize, since this means we are
----------------
getFixedSize():?  (etc.; please go through the whole patch.)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85743/new/

https://reviews.llvm.org/D85743