[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend

[Amy Kwan via Phabricator via cfe-commits]

amyk accepted this revision.
amyk added inline comments.
This revision is now accepted and ready to land.


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Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:703
+vector signed __int128 test_vec_xl_sext_i8(void) {
+  // CHECK: load i8
+  // CHECK: sext i8
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It would be good to be a little more specific with the CHECK lines. 


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13500
   SDValue Ext2 = N->getOperand(1).getOperand(0);
-  if(Ext1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
-     Ext2.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
+  if (Ext1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
+      Ext2.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
----------------
This line here and below looks like unintended changes from clang-format I am guessing? I am OK with them being removed during commit. 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82502/new/

https://reviews.llvm.org/D82502