[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13422
+ return DAG.getMemIntrinsicNode(PPCISD::LXVRZX, dl,
+                                DAG.getVTList(MVT::v1i128, MVT::Other),
+                                LoadOps, MemoryType, LD->getMemOperand());
----------------
please `clang-format` the changed files before updating the patch.  


================
Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll:4
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
-; RUN:   FileCheck %s
+; RUN: FileCheck %s --check-prefix=CHECK-LE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
----------------
Why do we need different check prefixes for `LE` and `BE`? They produce the same asm.  It seems we only need `CHECK-O0`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82502/new/

https://reviews.llvm.org/D82502