[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14156
+
+  // This transformation is only valid if the we are loading either a byte,
+  // halfword, word, or doubleword.
----------------
Conanap wrote:
> NeHuang wrote:
> > nit: if we are loading either a byte....
> I'm not too sure what you mean, would you be able to elaborate?  
> The comment is:
> 
> 
> > This transformation is only valid if the we are loading either a byte,
> > halfword, word, or doubleword.
> 
> Thanks!
> 
> 
Extra `the` in your sentence:
`This transformation is only valid if the we are loading` -> `This transformation is only valid if we are loading`


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82502/new/

https://reviews.llvm.org/D82502