[PATCH] D83551: [PATCH 2/4][Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

[Aaron Ballman via Phabricator via cfe-commits]

aaron.ballman accepted this revision.
aaron.ballman added a comment.
This revision is now accepted and ready to land.

The attribute bits LGTM, thanks!



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Comment at: clang/lib/AST/ASTContext.cpp:1887
+
+unsigned getSvePredWidth(const Type *T) { return getSveVectorWidth(T) / 8; }
+
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c-rhodes wrote:
> aaron.ballman wrote:
> > Should this be dividing by the number of bits in a char for the target as opposed to hard-coding to 8?
> > Should this be dividing by the number of bits in a char for the target as opposed to hard-coding to 8?
> 
> Predicate registers in SVE hold one bit per byte of a vector register so each predicate is 1/8th the size of a vector which are defined in bits, it has to be 8 and I know `getCharWidth` returns 8 for the target this is implemented for but I dont know what it would mean for any other target or if we care about that?
Ah, so this is a case where we expect that value to always be 8 where this feature is supported anyway -- good to know. I still think the current code is a cleaner approach to hard-coding 8 bits, so thank you for making the change even though it doesn't enable much.


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https://reviews.llvm.org/D83551