[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

[Victor Huang via Phabricator via cfe-commits]

NeHuang added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14156
+
+  // This transformation is only valid if the we are loading either a byte,
+  // halfword, word, or doubleword.
----------------
nit: if we are loading either a byte....


================
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:29
+                       [SDNPHasChain, SDNPMayLoad]>;
+
+
----------------
nit: one space is enough.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82502/new/

https://reviews.llvm.org/D82502