[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute
Cullen Rhodes via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Thu Jul 16 07:21:05 PDT 2020
c-rhodes marked 5 inline comments as done.
c-rhodes added inline comments.
================
Comment at: clang/lib/CodeGen/CodeGenTypes.h:138
+ llvm::Type *ConvertTypeForMem(QualType T, bool ForBitField = false,
+ bool EnforceFixedLengthSVEAttribute = false);
----------------
efriedma wrote:
> The default for EnforceFixedLengthSVEAttribute seems backwards; I would expect that almost everywhere that calls ConvertTypeForMem actually wants the fixed-length type. The scalable type only exists in registers.
> The default for EnforceFixedLengthSVEAttribute seems backwards; I would expect that almost everywhere that calls ConvertTypeForMem actually wants the fixed-length type. The scalable type only exists in registers.
It has no effect unless `T->isVLST()` so I think it makes sense.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D83553/new/
https://reviews.llvm.org/D83553
More information about the cfe-commits
mailing list