[clang] fc55308 - [PowerPC][Power10] Fix VINS* (vector insert byte/half/word) instructions to have i32 arguments.
Amy Kwan via cfe-commits
cfe-commits at lists.llvm.org
Wed Jul 15 22:31:23 PDT 2020
Author: Amy Kwan
Date: 2020-07-16T00:30:24-05:00
New Revision: fc55308628709bfc64b100dadf9a030fbb2afaee
URL: https://github.com/llvm/llvm-project/commit/fc55308628709bfc64b100dadf9a030fbb2afaee
DIFF: https://github.com/llvm/llvm-project/commit/fc55308628709bfc64b100dadf9a030fbb2afaee.diff
LOG: [PowerPC][Power10] Fix VINS* (vector insert byte/half/word) instructions to have i32 arguments.
Previously, the vins* intrinsic was incorrectly defined to have its second and
third argument arguments as an i64. This patch fixes the second and third
argument of the vins* instruction and intrinsic to have i32s instead.
Differential Revision: https://reviews.llvm.org/D83497
Added:
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def
index 6b291e6b0806..5d445c253a85 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -321,12 +321,12 @@ BUILTIN(__builtin_altivec_vsldbi, "V16UcV16UcV16UcIi", "")
BUILTIN(__builtin_altivec_vsrdbi, "V16UcV16UcV16UcIi", "")
// P10 Vector Insert built-ins.
-BUILTIN(__builtin_altivec_vinsblx, "V16UcV16UcULLiULLi", "")
-BUILTIN(__builtin_altivec_vinsbrx, "V16UcV16UcULLiULLi", "")
-BUILTIN(__builtin_altivec_vinshlx, "V8UsV8UsULLiULLi", "")
-BUILTIN(__builtin_altivec_vinshrx, "V8UsV8UsULLiULLi", "")
-BUILTIN(__builtin_altivec_vinswlx, "V4UiV4UiULLiULLi", "")
-BUILTIN(__builtin_altivec_vinswrx, "V4UiV4UiULLiULLi", "")
+BUILTIN(__builtin_altivec_vinsblx, "V16UcV16UcUiUi", "")
+BUILTIN(__builtin_altivec_vinsbrx, "V16UcV16UcUiUi", "")
+BUILTIN(__builtin_altivec_vinshlx, "V8UsV8UsUiUi", "")
+BUILTIN(__builtin_altivec_vinshrx, "V8UsV8UsUiUi", "")
+BUILTIN(__builtin_altivec_vinswlx, "V4UiV4UiUiUi", "")
+BUILTIN(__builtin_altivec_vinswrx, "V4UiV4UiUiUi", "")
BUILTIN(__builtin_altivec_vinsdlx, "V2ULLiV2ULLiULLiULLi", "")
BUILTIN(__builtin_altivec_vinsdrx, "V2ULLiV2ULLiULLiULLi", "")
BUILTIN(__builtin_altivec_vinsbvlx, "V16UcV16UcULLiV16Uc", "")
diff --git a/clang/test/CodeGen/builtins-ppc-p10vector.c b/clang/test/CodeGen/builtins-ppc-p10vector.c
index c51c24f25986..4e804fbafb30 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -402,25 +402,25 @@ vector double test_vec_blend_d(void) {
}
vector unsigned char test_vec_insertl_uc(void) {
- // CHECK-BE: @llvm.ppc.altivec.vinsblx(<16 x i8> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-BE: @llvm.ppc.altivec.vinsblx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32
// CHECK-BE-NEXT: ret <16 x i8>
- // CHECK-LE: @llvm.ppc.altivec.vinsbrx(<16 x i8> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-LE: @llvm.ppc.altivec.vinsbrx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32
// CHECK-LE-NEXT: ret <16 x i8>
return vec_insertl(uca, vuca, uia);
}
vector unsigned short test_vec_insertl_us(void) {
- // CHECK-BE: @llvm.ppc.altivec.vinshlx(<8 x i16> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-BE: @llvm.ppc.altivec.vinshlx(<8 x i16> %{{.+}}, i32 %{{.+}}, i32
// CHECK-BE-NEXT: ret <8 x i16>
- // CHECK-LE: @llvm.ppc.altivec.vinshrx(<8 x i16> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-LE: @llvm.ppc.altivec.vinshrx(<8 x i16> %{{.+}}, i32 %{{.+}}, i32
// CHECK-LE-NEXT: ret <8 x i16>
return vec_insertl(usa, vusa, uia);
}
vector unsigned int test_vec_insertl_ui(void) {
- // CHECK-BE: @llvm.ppc.altivec.vinswlx(<4 x i32> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-BE: @llvm.ppc.altivec.vinswlx(<4 x i32> %{{.+}}, i32 %{{.+}}, i32
// CHECK-BE-NEXT: ret <4 x i32>
- // CHECK-LE: @llvm.ppc.altivec.vinswrx(<4 x i32> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-LE: @llvm.ppc.altivec.vinswrx(<4 x i32> %{{.+}}, i32 %{{.+}}, i32
// CHECK-LE-NEXT: ret <4 x i32>
return vec_insertl(uib, vuia, uia);
}
@@ -458,25 +458,25 @@ vector unsigned int test_vec_insertl_uiv(void) {
}
vector unsigned char test_vec_inserth_uc(void) {
- // CHECK-BE: @llvm.ppc.altivec.vinsbrx(<16 x i8> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-BE: @llvm.ppc.altivec.vinsbrx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32
// CHECK-BE-NEXT: ret <16 x i8>
- // CHECK-LE: @llvm.ppc.altivec.vinsblx(<16 x i8> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-LE: @llvm.ppc.altivec.vinsblx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32
// CHECK-LE-NEXT: ret <16 x i8>
return vec_inserth(uca, vuca, uia);
}
vector unsigned short test_vec_inserth_us(void) {
- // CHECK-BE: @llvm.ppc.altivec.vinshrx(<8 x i16> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-BE: @llvm.ppc.altivec.vinshrx(<8 x i16> %{{.+}}, i32 %{{.+}}, i32
// CHECK-BE-NEXT: ret <8 x i16>
- // CHECK-LE: @llvm.ppc.altivec.vinshlx(<8 x i16> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-LE: @llvm.ppc.altivec.vinshlx(<8 x i16> %{{.+}}, i32 %{{.+}}, i32
// CHECK-LE-NEXT: ret <8 x i16>
return vec_inserth(usa, vusa, uia);
}
vector unsigned int test_vec_inserth_ui(void) {
- // CHECK-BE: @llvm.ppc.altivec.vinswrx(<4 x i32> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-BE: @llvm.ppc.altivec.vinswrx(<4 x i32> %{{.+}}, i32 %{{.+}}, i32
// CHECK-BE-NEXT: ret <4 x i32>
- // CHECK-LE: @llvm.ppc.altivec.vinswlx(<4 x i32> %{{.+}}, i64 %{{.+}}, i64
+ // CHECK-LE: @llvm.ppc.altivec.vinswlx(<4 x i32> %{{.+}}, i32 %{{.+}}, i32
// CHECK-LE-NEXT: ret <4 x i32>
return vec_inserth(uib, vuia, uia);
}
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 614a29049686..2abb6b4e55fe 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -468,27 +468,27 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
// P10 Vector Insert.
def int_ppc_altivec_vinsblx : GCCBuiltin<"__builtin_altivec_vinsblx">,
Intrinsic<[llvm_v16i8_ty],
- [llvm_v16i8_ty, llvm_i64_ty, llvm_i64_ty],
+ [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem]>;
def int_ppc_altivec_vinsbrx : GCCBuiltin<"__builtin_altivec_vinsbrx">,
Intrinsic<[llvm_v16i8_ty],
- [llvm_v16i8_ty, llvm_i64_ty, llvm_i64_ty],
+ [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem]>;
def int_ppc_altivec_vinshlx : GCCBuiltin<"__builtin_altivec_vinshlx">,
Intrinsic<[llvm_v8i16_ty],
- [llvm_v8i16_ty, llvm_i64_ty, llvm_i64_ty],
+ [llvm_v8i16_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem]>;
def int_ppc_altivec_vinshrx : GCCBuiltin<"__builtin_altivec_vinshrx">,
Intrinsic<[llvm_v8i16_ty],
- [llvm_v8i16_ty, llvm_i64_ty, llvm_i64_ty],
+ [llvm_v8i16_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem]>;
def int_ppc_altivec_vinswlx : GCCBuiltin<"__builtin_altivec_vinswlx">,
Intrinsic<[llvm_v4i32_ty],
- [llvm_v4i32_ty, llvm_i64_ty, llvm_i64_ty],
+ [llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem]>;
def int_ppc_altivec_vinswrx : GCCBuiltin<"__builtin_altivec_vinswrx">,
Intrinsic<[llvm_v4i32_ty],
- [llvm_v4i32_ty, llvm_i64_ty, llvm_i64_ty],
+ [llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem]>;
def int_ppc_altivec_vinsdlx : GCCBuiltin<"__builtin_altivec_vinsdlx">,
Intrinsic<[llvm_v2i64_ty],
@@ -525,7 +525,7 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
// P10 Vector Insert with immediate.
def int_ppc_altivec_vinsw :
Intrinsic<[llvm_v4i32_ty],
- [llvm_v4i32_ty, llvm_i64_ty, llvm_i32_ty],
+ [llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<2>>]>;
def int_ppc_altivec_vinsd :
Intrinsic<[llvm_v2i64_ty],
diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index 2bab73418e10..1759570469e8 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -242,15 +242,6 @@ class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
}
-// VX-Form: [PO VRT / UIM RB XO].
-// We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent
-// "/ UIM" (unused bit followed by a 4-bit immediate)
-// Destructive (insert) forms are suffixed with _ins.
-class VXForm_VRT5_UIM5_RB5_ins<bits<11> xo, string opc, list<dag> pattern>
- : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, g8rc:$rB),
- !strconcat(opc, " $vD, $rB, $UIM"), IIC_VecGeneral, pattern>,
- RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
-
// VX-Form: [PO VRT RA VRB XO].
// Destructive (insert) forms are suffixed with _ins.
class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern>
@@ -261,7 +252,7 @@ class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern>
// VX-Form: [PO VRT RA RB XO].
// Destructive (insert) forms are suffixed with _ins.
class VXForm_VRT5_RAB5_ins<bits<11> xo, string opc, list<dag> pattern>
- : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB),
+ : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, gprc:$rB),
!strconcat(opc, " $vD, $rA, $rB"), IIC_VecGeneral, pattern>,
RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
@@ -813,16 +804,18 @@ let Predicates = [IsISA3_1] in {
(int_ppc_altivec_vsrdbi v16i8:$VRA,
v16i8:$VRB,
i32:$SH))]>;
- def VINSW :
- VXForm_VRT5_UIM5_RB5_ins<207, "vinsw",
- [(set v4i32:$vD,
- (int_ppc_altivec_vinsw v4i32:$vDi, i64:$rB,
- timm:$UIM))]>;
+ def VINSW :
+ VXForm_1<207, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, gprc:$rB),
+ "vinsw $vD, $rB, $UIM", IIC_VecGeneral,
+ [(set v4i32:$vD,
+ (int_ppc_altivec_vinsw v4i32:$vDi, i32:$rB, timm:$UIM))]>,
+ RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
def VINSD :
- VXForm_VRT5_UIM5_RB5_ins<463, "vinsd",
- [(set v2i64:$vD,
- (int_ppc_altivec_vinsd v2i64:$vDi, i64:$rB,
- timm:$UIM))]>;
+ VXForm_1<463, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, g8rc:$rB),
+ "vinsd $vD, $rB, $UIM", IIC_VecGeneral,
+ [(set v2i64:$vD,
+ (int_ppc_altivec_vinsd v2i64:$vDi, i64:$rB, timm:$UIM))]>,
+ RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
def VINSBVLX :
VXForm_VTB5_RA5_ins<15, "vinsbvlx",
[(set v16i8:$vD,
@@ -856,44 +849,45 @@ let Predicates = [IsISA3_1] in {
def VINSBLX :
VXForm_VRT5_RAB5_ins<527, "vinsblx",
[(set v16i8:$vD,
- (int_ppc_altivec_vinsblx v16i8:$vDi, i64:$rA,
- i64:$rB))]>;
+ (int_ppc_altivec_vinsblx v16i8:$vDi, i32:$rA,
+ i32:$rB))]>;
def VINSBRX :
VXForm_VRT5_RAB5_ins<783, "vinsbrx",
[(set v16i8:$vD,
- (int_ppc_altivec_vinsbrx v16i8:$vDi, i64:$rA,
- i64:$rB))]>;
+ (int_ppc_altivec_vinsbrx v16i8:$vDi, i32:$rA,
+ i32:$rB))]>;
def VINSHLX :
VXForm_VRT5_RAB5_ins<591, "vinshlx",
[(set v8i16:$vD,
- (int_ppc_altivec_vinshlx v8i16:$vDi, i64:$rA,
- i64:$rB))]>;
+ (int_ppc_altivec_vinshlx v8i16:$vDi, i32:$rA,
+ i32:$rB))]>;
def VINSHRX :
VXForm_VRT5_RAB5_ins<847, "vinshrx",
[(set v8i16:$vD,
- (int_ppc_altivec_vinshrx v8i16:$vDi, i64:$rA,
- i64:$rB))]>;
+ (int_ppc_altivec_vinshrx v8i16:$vDi, i32:$rA,
+ i32:$rB))]>;
def VINSWLX :
VXForm_VRT5_RAB5_ins<655, "vinswlx",
[(set v4i32:$vD,
- (int_ppc_altivec_vinswlx v4i32:$vDi, i64:$rA,
- i64:$rB))]>;
+ (int_ppc_altivec_vinswlx v4i32:$vDi, i32:$rA,
+ i32:$rB))]>;
def VINSWRX :
VXForm_VRT5_RAB5_ins<911, "vinswrx",
[(set v4i32:$vD,
- (int_ppc_altivec_vinswrx v4i32:$vDi, i64:$rA,
- i64:$rB))]>;
+ (int_ppc_altivec_vinswrx v4i32:$vDi, i32:$rA,
+ i32:$rB))]>;
def VINSDLX :
- VXForm_VRT5_RAB5_ins<719, "vinsdlx",
- [(set v2i64:$vD,
- (int_ppc_altivec_vinsdlx v2i64:$vDi, i64:$rA,
- i64:$rB))]>;
+ VXForm_1<719, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB),
+ "vinsdlx $vD, $rA, $rB", IIC_VecGeneral,
+ [(set v2i64:$vD,
+ (int_ppc_altivec_vinsdlx v2i64:$vDi, i64:$rA, i64:$rB))]>,
+ RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
def VINSDRX :
- VXForm_VRT5_RAB5_ins<975, "vinsdrx",
- [(set v2i64:$vD,
- (int_ppc_altivec_vinsdrx v2i64:$vDi, i64:$rA,
- i64:$rB))]>;
-
+ VXForm_1<975, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB),
+ "vinsdrx $vD, $rA, $rB", IIC_VecGeneral,
+ [(set v2i64:$vD,
+ (int_ppc_altivec_vinsdrx v2i64:$vDi, i64:$rA, i64:$rB))]>,
+ RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vpdepd $vD, $vA, $vB", IIC_VecGeneral,
[(set v2i64:$vD,
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
index 84bf4032aa34..3e4a509dc943 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
@@ -82,71 +82,71 @@ entry:
}
declare <2 x i64> @llvm.ppc.vsx.xxblendvd(<2 x i64>, <2 x i64>, <2 x i64>)
-define <16 x i8> @testVINSBLX(<16 x i8> %a, i64 %b, i64 %c) {
+define <16 x i8> @testVINSBLX(<16 x i8> %a, i32 %b, i32 %c) {
; CHECK-LABEL: testVINSBLX:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinsblx v2, r5, r6
; CHECK-NEXT: blr
entry:
- %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsblx(<16 x i8> %a, i64 %b, i64 %c)
+ %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsblx(<16 x i8> %a, i32 %b, i32 %c)
ret <16 x i8> %0
}
-declare <16 x i8> @llvm.ppc.altivec.vinsblx(<16 x i8>, i64, i64)
+declare <16 x i8> @llvm.ppc.altivec.vinsblx(<16 x i8>, i32, i32)
-define <16 x i8> @testVINSBRX(<16 x i8> %a, i64 %b, i64 %c) {
+define <16 x i8> @testVINSBRX(<16 x i8> %a, i32 %b, i32 %c) {
; CHECK-LABEL: testVINSBRX:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinsbrx v2, r5, r6
; CHECK-NEXT: blr
entry:
- %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbrx(<16 x i8> %a, i64 %b, i64 %c)
+ %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbrx(<16 x i8> %a, i32 %b, i32 %c)
ret <16 x i8> %0
}
-declare <16 x i8> @llvm.ppc.altivec.vinsbrx(<16 x i8>, i64, i64)
+declare <16 x i8> @llvm.ppc.altivec.vinsbrx(<16 x i8>, i32, i32)
-define <8 x i16> @testVINSHLX(<8 x i16> %a, i64 %b, i64 %c) {
+define <8 x i16> @testVINSHLX(<8 x i16> %a, i32 %b, i32 %c) {
; CHECK-LABEL: testVINSHLX:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinshlx v2, r5, r6
; CHECK-NEXT: blr
entry:
- %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshlx(<8 x i16> %a, i64 %b, i64 %c)
+ %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshlx(<8 x i16> %a, i32 %b, i32 %c)
ret <8 x i16> %0
}
-declare <8 x i16> @llvm.ppc.altivec.vinshlx(<8 x i16>, i64, i64)
+declare <8 x i16> @llvm.ppc.altivec.vinshlx(<8 x i16>, i32, i32)
-define <8 x i16> @testVINSHRX(<8 x i16> %a, i64 %b, i64 %c) {
+define <8 x i16> @testVINSHRX(<8 x i16> %a, i32 %b, i32 %c) {
; CHECK-LABEL: testVINSHRX:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinshrx v2, r5, r6
; CHECK-NEXT: blr
entry:
- %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshrx(<8 x i16> %a, i64 %b, i64 %c)
+ %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshrx(<8 x i16> %a, i32 %b, i32 %c)
ret <8 x i16> %0
}
-declare <8 x i16> @llvm.ppc.altivec.vinshrx(<8 x i16>, i64, i64)
+declare <8 x i16> @llvm.ppc.altivec.vinshrx(<8 x i16>, i32, i32)
-define <4 x i32> @testVINSWLX(<4 x i32> %a, i64 %b, i64 %c) {
+define <4 x i32> @testVINSWLX(<4 x i32> %a, i32 %b, i32 %c) {
; CHECK-LABEL: testVINSWLX:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinswlx v2, r5, r6
; CHECK-NEXT: blr
entry:
- %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswlx(<4 x i32> %a, i64 %b, i64 %c)
+ %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswlx(<4 x i32> %a, i32 %b, i32 %c)
ret <4 x i32> %0
}
-declare <4 x i32> @llvm.ppc.altivec.vinswlx(<4 x i32>, i64, i64)
+declare <4 x i32> @llvm.ppc.altivec.vinswlx(<4 x i32>, i32, i32)
-define <4 x i32> @testVINSWRX(<4 x i32> %a, i64 %b, i64 %c) {
+define <4 x i32> @testVINSWRX(<4 x i32> %a, i32 %b, i32 %c) {
; CHECK-LABEL: testVINSWRX:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinswrx v2, r5, r6
; CHECK-NEXT: blr
entry:
- %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswrx(<4 x i32> %a, i64 %b, i64 %c)
+ %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswrx(<4 x i32> %a, i32 %b, i32 %c)
ret <4 x i32> %0
}
-declare <4 x i32> @llvm.ppc.altivec.vinswrx(<4 x i32>, i64, i64)
+declare <4 x i32> @llvm.ppc.altivec.vinswrx(<4 x i32>, i32, i32)
define <2 x i64> @testVINSDLX(<2 x i64> %a, i64 %b, i64 %c) {
; CHECK-LABEL: testVINSDLX:
@@ -232,16 +232,16 @@ entry:
}
declare <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32>, i64, <4 x i32>)
-define <4 x i32> @testVINSW(<4 x i32> %a, i64 %b) {
+define <4 x i32> @testVINSW(<4 x i32> %a, i32 %b) {
; CHECK-LABEL: testVINSW:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinsw v2, r5, 1
; CHECK-NEXT: blr
entry:
- %0 = tail call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> %a, i64 %b, i32 1)
+ %0 = tail call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> %a, i32 %b, i32 1)
ret <4 x i32> %0
}
-declare <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32>, i64, i32 immarg)
+declare <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32>, i32, i32 immarg)
define <2 x i64> @testVINSD(<2 x i64> %a, i64 %b) {
; CHECK-LABEL: testVINSD:
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