[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

[Eli Friedman via Phabricator via cfe-commits]

efriedma added a comment.

In D83553#2151591 <https://reviews.llvm.org/D83553#2151591>, @sdesmalen wrote:

> In D83553#2148429 <https://reviews.llvm.org/D83553#2148429>, @efriedma wrote:
>
> > > If you mean alloca's for single vectors
> >
> > I was really referring to the IR values themselves, not the memory representation.  Since the width of the vectors is known, you could emit IR without any mention of scalable types at all (assuming the backend was extended to handle the intrinsics).
>
>
> That's right, the reason is because codegen of the intrinsics currently only works on scalable types. By casting the pointer to a vscale-pointer, all IR values are always scalable so we don't need to worry about doing things like reinterpet_cast from a scalable to fixed-width vector, or vice versa.


I guess that's reasonable.  I suspect we're eventually going to end up with that functionality anyway, but maybe not right now.



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Comment at: clang/lib/CodeGen/CodeGenTypes.h:138
+  llvm::Type *ConvertTypeForMem(QualType T, bool ForBitField = false,
+                                bool EnforceFixedLengthSVEAttribute = false);
 
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The default for EnforceFixedLengthSVEAttribute seems backwards; I would expect that almost everywhere that calls ConvertTypeForMem actually wants the fixed-length type.  The scalable type only exists in registers.


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