[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

[Eli Friedman via Phabricator via cfe-commits]

efriedma added a comment.

> If you mean alloca's for single vectors

I was really referring to the IR values themselves, not the memory representation.  Since the width of the vectors is known, you could emit IR without any mention of scalable types at all (assuming the backend was extended to handle the intrinsics).

The choice of vscale'ed types for variables is also interesting, though. Thanks for the explanation.


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https://reviews.llvm.org/D83553