[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, rsandifo-arm, efriedma, cameron.mcinally, ctetreau.
Herald added subscribers: danielkiss, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: clang.

This patch implements codegen for the 'arm_sve_vector_bits' type
attribute, defined by the Arm C Language Extensions (ACLE) for SVE [1].
The purpose of this attribute is to define fixed-length (VLST) versions
of existing sizeless types (VLAT).

Implemented in this patch is the lowering of VLSTs to valid types.
VLSTs (unlike VLATs) can be used in globals, members of structs
and unions, and arrays. To support this in this patch we lower VLSTs to
arrays. For example, in the following C code:

  #if __ARM_FEATURE_SVE_BITS==512
  typedef svint32_t fixed_svint32_t __attribute__((arm_sve_vector_bits(512)));
  struct struct_int32 {
    fixed_int32_t x;
  } struct_int32;
  #endif

the struct is lowered to:

  %struct.struct_int32 = type { [16 x i32] }

where the member 'x' is a fixed-length variant of 'svint32_t' that
contains exactly 512 bits.

When loading from a VLST to a VLAT, or when storing a VLAT to a VLST,
the address is bitcasted, e.g.

  bitcast [N x i8]* %addr.ptr to <vscale x 16 x i8>*

[1] https://developer.arm.com/documentation/100987/latest


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83553

Files:
  clang/lib/CodeGen/CGExpr.cpp
  clang/lib/CodeGen/CGRecordLayoutBuilder.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/CodeGenTypes.h
  clang/test/Sema/attr-arm-sve-vector-bits-bitcast.c
  clang/test/Sema/attr-arm-sve-vector-bits-call.c
  clang/test/Sema/attr-arm-sve-vector-bits-cast.c
  clang/test/Sema/attr-arm-sve-vector-bits-codegen.c
  clang/test/Sema/attr-arm-sve-vector-bits-globals.c
  clang/test/Sema/attr-arm-sve-vector-bits-types.c

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