[PATCH] D83364: [PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend

[Albion Fung via Phabricator via cfe-commits]

Conanap marked 2 inline comments as done.
Conanap added a comment.

Relocated the isntr definitions to a more appropriate place.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83364/new/

https://reviews.llvm.org/D83364