[PATCH] D83364: [PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend

[Lei Huang via Phabricator via cfe-commits]

lei added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:431
 
+let mayLoad = 1, mayStore = 0, Predicates = [IsISA3_1] in {
+  // The XFormMemOp flag is set on the instruction format.
----------------
Instead of creating a new section like this, why not add to the existing one on line 469?  I realize that does not have `Predicates = [IsISA3_1]`, but I think that is an oversight from previous patch and it should be added as those instructions are also part of ISA3.1.


================
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:439
+
+let mayLoad = 0, mayStore = 1, Predicates = [IsISA3_1] in {
+  // The XFormMemOp flag is set on the instruction format.
----------------
same.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83364/new/

https://reviews.llvm.org/D83364