[PATCH] D83364: [PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend

[Albion Fung via Phabricator via cfe-commits]

Conanap created this revision.
Conanap added reviewers: power-llvm-team, PowerPC, saghir, nemanjai, hfinkel.
Conanap added projects: LLVM, clang, PowerPC.

Includes instruction defintion and MC Tests for above instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83364

Files:
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
  llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s


Index: llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
===================================================================
--- llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
+++ llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
@@ -405,3 +405,27 @@
 # CHECK-BE: vinsdrx 1, 2, 3                       # encoding: [0x10,0x22,0x1b,0xcf]
 # CHECK-LE: vinsdrx 1, 2, 3                       # encoding: [0xcf,0x1b,0x22,0x10]
             vinsdrx 1, 2, 3
+# CHECK-BE: lxvrbx 32, 1, 2                       # encoding: [0x7c,0x01,0x10,0x1b]
+# CHECK-LE: lxvrbx 32, 1, 2                       # encoding: [0x1b,0x10,0x01,0x7c]
+            lxvrbx 32, 1, 2
+# CHECK-BE: lxvrhx 33, 1, 2                       # encoding: [0x7c,0x21,0x10,0x5b]
+# CHECK-LE: lxvrhx 33, 1, 2                       # encoding: [0x5b,0x10,0x21,0x7c]
+            lxvrhx 33, 1, 2
+# CHECK-BE: lxvrdx 34, 1, 2                       # encoding: [0x7c,0x41,0x10,0xdb]
+# CHECK-LE: lxvrdx 34, 1, 2                       # encoding: [0xdb,0x10,0x41,0x7c]
+            lxvrdx 34, 1, 2
+# CHECK-BE: lxvrwx 35, 1, 2                       # encoding: [0x7c,0x61,0x10,0x9b]
+# CHECK-LE: lxvrwx 35, 1, 2                       # encoding: [0x9b,0x10,0x61,0x7c]
+            lxvrwx 35, 1, 2
+# CHECK-BE: stxvrbx 32, 3, 1                      # encoding: [0x7c,0x03,0x09,0x1b]
+# CHECK-LE: stxvrbx 32, 3, 1                      # encoding: [0x1b,0x09,0x03,0x7c]
+            stxvrbx 32, 3, 1
+# CHECK-BE: stxvrhx 33, 3, 1                      # encoding: [0x7c,0x23,0x09,0x5b]
+# CHECK-LE: stxvrhx 33, 3, 1                      # encoding: [0x5b,0x09,0x23,0x7c]
+            stxvrhx 33, 3, 1
+# CHECK-BE: stxvrwx 34, 3, 1                      # encoding: [0x7c,0x43,0x09,0x9b]
+# CHECK-LE: stxvrwx 34, 3, 1                      # encoding: [0x9b,0x09,0x43,0x7c]
+            stxvrwx 34, 3, 1
+# CHECK-BE: stxvrdx 35, 3, 1                      # encoding: [0x7c,0x63,0x09,0xdb]
+# CHECK-LE: stxvrdx 35, 3, 1                      # encoding: [0xdb,0x09,0x63,0x7c]
+            stxvrdx 35, 3, 1
Index: llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
===================================================================
--- llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
+++ llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
@@ -278,3 +278,27 @@
 
 # CHECK: vinsdrx 1, 2, 3
 0x10 0x22 0x1b 0xcf
+
+# CHECK: lxvrbx 32, 1, 2
+0x7c 0x01 0x10 0x1b
+
+# CHECK: lxvrhx 33, 1, 2
+0x7c 0x21 0x10 0x5b
+
+# CHECK: lxvrdx 34, 1, 2
+0x7c 0x41 0x10 0xdb
+
+# CHECK: lxvrwx 35, 1, 2
+0x7c 0x61 0x10 0x9b
+
+# CHECK: stxvrbx 32, 3, 1
+0x7c 0x03 0x09 0x1b
+
+# CHECK: stxvrhx 33, 3, 1
+0x7c 0x23 0x09 0x5b
+
+# CHECK: stxvrwx 34, 3, 1
+0x7c 0x43 0x09 0x9b
+
+# CHECK: stxvrdx 35, 3, 1
+0x7c 0x63 0x09 0xdb
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -428,6 +428,22 @@
 def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
 def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
 
+let mayLoad = 1, mayStore = 0, Predicates = [IsISA3_1] in {
+  // The XFormMemOp flag is set on the instruction format.
+  def LXVRBX : X_XT6_RA5_RB5<31, 13, "lxvrbx", vsrc, []>;
+  def LXVRHX : X_XT6_RA5_RB5<31, 45, "lxvrhx", vsrc, []>;
+  def LXVRWX : X_XT6_RA5_RB5<31, 77, "lxvrwx", vsrc, []>;
+  def LXVRDX : X_XT6_RA5_RB5<31, 109, "lxvrdx", vsrc, []>;
+}
+
+let mayLoad = 0, mayStore = 1, Predicates = [IsISA3_1] in {
+  // The XFormMemOp flag is set on the instruction format.
+  def STXVRBX : X_XS6_RA5_RB5<31, 141, "stxvrbx", vsrc, []>;
+  def STXVRHX : X_XS6_RA5_RB5<31, 173, "stxvrhx", vsrc, []>;
+  def STXVRWX : X_XS6_RA5_RB5<31, 205, "stxvrwx", vsrc, []>;
+  def STXVRDX : X_XS6_RA5_RB5<31, 237, "stxvrdx", vsrc, []>;
+}
+
 let Predicates = [PrefixInstrs] in {
   let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
     defm PADDI8 :


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