[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend
Albion Fung via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Thu Jun 25 10:14:17 PDT 2020
Conanap updated this revision to Diff 273421.
Conanap marked 9 inline comments as done.
Conanap added a comment.
Fixed return signature for the open coded functions in altivec.h
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82502/new/
https://reviews.llvm.org/D82502
Files:
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll
llvm/test/MC/Disassembler/PowerPC/p10insts.txt
llvm/test/MC/PowerPC/p10.s
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