[PATCH] D69987: [RISCV] Assemble/Disassemble v-ext instructions.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai marked an inline comment as done.
HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:9
+///
+/// This file describes the RISC-V instructions from the standard 'V',
+/// Vector instruction set extension.
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asb wrote:
> Please add similar language as in RISCVInstrInfoB.td to indicate the version being described and explain this version is experimental and hasn't been ratified.
Got it. I will add more comments similar to RISCVInstrInfoB.td before landing the patch.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D69987/new/

https://reviews.llvm.org/D69987