[PATCH] D82448: [AArch64][SVE] Add bfloat16 support to store intrinsics
Kerry McLaughlin via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Thu Jun 25 06:53:23 PDT 2020
kmclaughlin updated this revision to Diff 273331.
kmclaughlin added a comment.
- Added HasSVE to Predicates in AArch64SVEInstrInfo.td
- Removed unnecessary indentation changes in AArch64SVEInstrInfo.td
- Removed hasBF16 variable from performST1Combine/performSTNT1Combine
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82448/new/
https://reviews.llvm.org/D82448
Files:
clang/include/clang/Basic/arm_sve.td
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_stnt1-bfloat.c
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/sve-intrinsics-st1-addressing-mode-reg-imm.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-st1-addressing-mode-reg-reg.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-st1.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
llvm/test/CodeGen/AArch64/sve-masked-ldst-nonext.ll
llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll
llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll
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