[PATCH] D82182: [AArch64][SVE] Add bfloat16 support to perm and select intrinsics

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll:809
 
+define <vscale x 8 x bfloat> @rev_bf16(<vscale x 8 x bfloat> %a) {
+; CHECK-LABEL: rev_bf16
----------------
sdesmalen wrote:
> Does this test not need the `+bf16` attribute to work? (which implies the patterns are missing the right predicate)
It should do, sorry I missed that. I've tried:
```diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 46cca2a..5ab2502 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -1124,10 +1124,13 @@ multiclass sve_int_perm_reverse_z<string asm, SDPatternOperator op> {
   def : SVE_1_Op_Pat<nxv4i32, op, nxv4i32, !cast<Instruction>(NAME # _S)>;
   def : SVE_1_Op_Pat<nxv2i64, op, nxv2i64, !cast<Instruction>(NAME # _D)>;

-  def : SVE_1_Op_Pat<nxv8bf16, op, nxv8bf16, !cast<Instruction>(NAME # _H)>;
   def : SVE_1_Op_Pat<nxv8f16,  op, nxv8f16,  !cast<Instruction>(NAME # _H)>;
   def : SVE_1_Op_Pat<nxv4f32,  op, nxv4f32,  !cast<Instruction>(NAME # _S)>;
   def : SVE_1_Op_Pat<nxv2f64,  op, nxv2f64,  !cast<Instruction>(NAME # _D)>;
+
+  let Predicates = [HasBF16] in {
+    def : SVE_1_Op_Pat<nxv8bf16, op, nxv8bf16, !cast<Instruction>(NAME # _H)>;
+  }
 }```

but this still works without `+bf16`. I noticed in your patch D82187 you check `Subtarget->hasBF16()` for `MVT::nxv8bf16` at select phase of ISEL, I guess it's different here with patterns. I also noticed we add the register class for `MVT::nxv8bf16` in AArch64ISelLowering without checking `Subtarget->hasBF16()` which I suspect is a bug. This test requires `+bf16` with that fixed but I wonder why the predicate isn't being recognised.


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https://reviews.llvm.org/D82182