[PATCH] D82298: [AArch64][SVE] Add bfloat16 support to load intrinsics

[Sander de Smalen via Phabricator via cfe-commits]

sdesmalen added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-ld1-addressing-mode-reg-imm.ll:217
+  %base_scalar = bitcast <vscale x 8 x bfloat>* %base to bfloat*
+  %load = call <vscale x 8 x bfloat> @llvm.aarch64.sve.ld1.nxv8bf16(<vscale x 8 x i1> %pg, bfloat* %base_scalar)
+  ret <vscale x 8 x bfloat> %load
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Sorry I only just spotted this in D82182 , but to match these intrinsics, the llc command needs to be passed +bf16 (and the patterns in the .td file need to be predicated accordingly)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82298/new/

https://reviews.llvm.org/D82298