[PATCH] D82182: [AArch64][SVE] Add bfloat16 support to perm and select intrinsics
Cullen Rhodes via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Fri Jun 19 10:19:18 PDT 2020
c-rhodes added inline comments.
================
Comment at: clang/include/clang/Basic/arm_sve.td:1115
+let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
+def SVREV_BF16 : SInst<"svrev[_{d}]", "dd", "b", MergeNone, "aarch64_sve_rev">;
----------------
fpetrogalli wrote:
> nit: could create a multiclass here like @sdesmalen have done in https://reviews.llvm.org/D82187, seems quite a nice way to keep the definition of the intrinsics together (look for `multiclass StructLoad`, for example)
it might be a bit tedious having separate multiclasses, what do you think about:
```multiclass SInstBF16<string n, string p, string t, MergeType mt, string i = "",
list<FlagType> ft = [], list<ImmCheck> ch = []> {
def : SInst<n, p, t, mt, i, ft, ch>;
let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
def : SInst<n, p, "b", mt, i, ft, ch>;
}
}
defm SVREV : SInstBF16<"svrev[_{d}]", "dd", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_rev">;
defm SVSEL : SInstBF16<"svsel[_{d}]", "dPdd", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_sel">;
defm SVSPLICE : SInstBF16<"svsplice[_{d}]", "dPdd", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_splice">;
defm SVTRN1 : SInstBF16<"svtrn1[_{d}]", "ddd", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_trn1">;
defm SVTRN2 : SInstBF16<"svtrn2[_{d}]", "ddd", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_trn2">;
defm SVUZP1 : SInstBF16<"svuzp1[_{d}]", "ddd", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_uzp1">;
defm SVUZP2 : SInstBF16<"svuzp2[_{d}]", "ddd", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_uzp2">;
defm SVZIP1 : SInstBF16<"svzip1[_{d}]", "ddd", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_zip1">;
defm SVZIP2 : SInstBF16<"svzip2[_{d}]", "ddd", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_zip2">;```
?
Repository:
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https://reviews.llvm.org/D82182/new/
https://reviews.llvm.org/D82182
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