[PATCH] D80970: [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector evaluate Builtins in LLVM/Clang

Lei Huang via Phabricator via cfe-commits cfe-commits at lists.llvm.org
Mon Jun 15 12:38:09 PDT 2020

Previous message: [PATCH] D80947: Add to the Coding Standard our that single-line bodies omit braces
Next message: [PATCH] D80935: [PowerPC][Power10] Implement Parallel Bits Deposit/Extract Builtins in LLVM/Clang
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

lei accepted this revision as: lei.
lei added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80970/new/

https://reviews.llvm.org/D80970

Previous message: [PATCH] D80947: Add to the Coding Standard our that single-line bodies omit braces
Next message: [PATCH] D80935: [PowerPC][Power10] Implement Parallel Bits Deposit/Extract Builtins in LLVM/Clang
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the cfe-commits mailing list