[PATCH] D80970: [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector evaluate Builtins in LLVM/Clang

[Anil Mahmud via Phabricator via cfe-commits]

anil9 added inline comments.


================
Comment at: clang/include/clang/Basic/BuiltinsPPC.def:305
 
+// P10 Vector Centrifuge
+BUILTIN(__builtin_altivec_vcfuged, "V2ULLiV2ULLiV2ULLi", "")
----------------
nit : // P10 Vector Centrifuge built-in.


================
Comment at: clang/include/clang/Basic/BuiltinsPPC.def:308
+
+// P10 Vector Gather Every N-th Bit
+BUILTIN(__builtin_altivec_vgnb, "ULLiV1ULLLiIi", "")
----------------
similar as above.


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Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:43
+  // CHECK-NEXT: ret i64
+  return vec_gnb(vui128a, 7);
+}
----------------
Try out some numbers which have different interpretation as signed/unsigned, if that matters that is.



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80970/new/

https://reviews.llvm.org/D80970