[PATCH] D79770: [RISCV] Fix passing two floating-point values in complex separately by two GPRs on RV64

Luís Marques via Phabricator via cfe-commits cfe-commits at lists.llvm.org
Tue May 12 02:07:05 PDT 2020


luismarques added inline comments.


================
Comment at: clang/lib/CodeGen/TargetInfo.cpp:10241-10242
   // Pass floating point values via FPRs if possible.
-  if (IsFixed && Ty->isFloatingType() && FLen >= Size && ArgFPRsLeft) {
+  if (IsFixed && Ty->isFloatingType() && !Ty->isComplexType() &&
+      FLen >= Size && ArgFPRsLeft) {
     ArgFPRsLeft--;
----------------
Do you have tests that show the impact of the added `FLen >= Size && ArgFPRsLeft` conditions for other values besides complex floats?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79770/new/

https://reviews.llvm.org/D79770





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